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Searched refs:PLLE_AUX (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1143 #define PLLE_AUX 0x48c macro
1166 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
1168 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
1244 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
1249 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
1255 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra30.c83 #define PLLE_AUX 0x48c macro
874 clk_base + PLLE_AUX, 2, 1, 0, NULL); in tegra30_pll_init()
1031 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1036 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
H A Dclk-tegra124.c62 #define PLLE_AUX 0x48c macro
479 .aux_reg = PLLE_AUX,
1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
H A Dclk-tegra210.c92 #define PLLE_AUX 0x48c macro
504 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_is_enabled()
527 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
530 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
535 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
1973 .aux_reg = PLLE_AUX,
3144 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3150 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
H A Dclk-tegra114.c93 #define PLLE_AUX 0x48c macro
563 .aux_reg = PLLE_AUX,
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c957 #define PLLE_AUX 0x48c macro
970 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
973 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()