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Searched refs:PCIE (Results 1 – 25 of 33) sorted by relevance

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/openbmc/u-boot/doc/
H A DREADME.srio-pcie-boot-corenet2 SRIO and PCIE Boot on Corenet Platforms
5 For some PowerPC processors with SRIO or PCIE interface, boot location can be
6 configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
8 from another processor's memory space by SRIO or PCIE link connected between
12 platforms and a RCW example with boot from SRIO or PCIE configuration.
14 Environment of the SRIO or PCIE boot:
16 b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
21 e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
22 the boot location to SRIO or PCIE, and holdoff all the cores.
27 | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
[all …]
/openbmc/qemu/docs/
H A Dpcie_pci_bridge.txt6 PCIE-to-PCI bridge is a new method for legacy PCI
12 PCIE-to-PCI bridge should now be used for any legacy PCI device usage
15 This generic PCIE-PCI bridge is a cross-platform device,
17 see 'PCIE-PCI bridge hot-plug' section),
25 PCIE-PCI bridge hot-plug
27 Guest OSes require extra efforts to enable PCIE-PCI bridge hot-plug.
36 that is planned to have PCIE-PCI bridge hot-plugged in.
89 - 2 PCIE-PCI bridges plugged into 2 different root ports;
92 - PCIE-PCI bridge, plugged into QEMU generic root port;
93 - 2 e1000 cards, one plugged into the cold-plugged PCIE-PCI bridge,
[all …]
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c174 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); in comphy_pcie_power_up()
179 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); in comphy_pcie_power_up()
184 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); in comphy_pcie_power_up()
189 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); in comphy_pcie_power_up()
194 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); in comphy_pcie_power_up()
199 reg_set16(phy_addr(PCIE, MISC_REG0), in comphy_pcie_power_up()
213 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); in comphy_pcie_power_up()
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); in comphy_pcie_power_up()
222 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, in comphy_pcie_power_up()
229 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); in comphy_pcie_power_up()
[all …]
H A Dcomphy_a3700.h74 PCIE = 1, enumerator
80 if (unit == PCIE) in phy_addr()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/aer-inject/
H A Daer-inject_1.0.bb1 SUMMARY = "Inject PCIE AER errors on the software level into a running Linux kernel."
3 aer-inject allows to inject PCIE AER errors on the software \
5 validation of the PCIE driver error recovery handler and \
6 PCIE AER core handler."
/openbmc/u-boot/board/freescale/lx2160a/
H A DREADME88 1 |Mezzanine:X-M4-PCIE-SGMII (29733)
91 |Mezzanine:X-M4-PCIE-SGMII (29733)
98 |Mezzanine:X-M4-PCIE-SGMII (29733)
105 |Mezzanine:X-M4-PCIE-SGMII (29733)
126 |Mezzanine:X-M4-PCIE-SGMII (29733)
133 |Mezzanine:X-M4-PCIE-SGMII (29733)
155 2 |Mezzanine:X-M6-PCIE-X8 (29737) *
160 3 |Mezzanine:X-M4-PCIE-SGMII (29733)
163 |Mezzanine:X-M4-PCIE-SGMII (29733)
167 5 |Mezzanine:X-M4-PCIE-SGMII (29733)
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dpinmux.c263 PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4),
264 PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4),
265 PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4),
266 PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4),
267 PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4),
268 PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4),
269 PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4),
270 PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4),
271 PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4),
272 PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
/openbmc/u-boot/board/nvidia/cardhu/
H A Dpinmux-config-cardhu.h267 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
268 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
269 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
270 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
272 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
273 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
274 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
275 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
276 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/openbmc/u-boot/board/avionic-design/common/
H A Dpinmux-config-tamonten-ng.h263 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
264 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
265 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
266 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
267 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
268 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
269 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
270 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
272 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/openbmc/u-boot/board/freescale/p1_p2_rdb_pc/
H A DREADME23 * PCIE slot and mini-PCIE slots
/openbmc/u-boot/board/toradex/colibri_t30/
H A Dpinmux-config-colibri_t30.h279 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
284 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
285 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
286 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
287 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
288 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
289 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
290 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/openbmc/u-boot/configs/
H A Dsbc8548_PCI_66_PCIE_defconfig8 CONFIG_SYS_EXTRA_OPTIONS="66,PCIE"
H A Dsbc8548_PCI_33_PCIE_defconfig8 CONFIG_SYS_EXTRA_OPTIONS="33,PCIE"
/openbmc/u-boot/board/freescale/c29xpcie/
H A DREADME34 0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
37 0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
/openbmc/qemu/docs/system/arm/
H A Draspi.rst44 * PCIE Root Port (raspi4b)
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zcu102-revA.dts154 output-low; /* PCIE = 0, DP = 1 */
160 output-high; /* PCIE = 0, DP = 1 */
166 output-high; /* PCIE = 0, USB0 = 1 */
172 output-high; /* PCIE = 0, SATA = 1 */
H A Dam57xx-idk-common.dtsi244 /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dpinmux.c304 PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
325 PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
328 PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
H A Dclock.c331 NONE(PCIE),
/openbmc/openbmc-test-automation/redfish/telemetry_service/
H A Dtest_telemetry_report.robot18 &{user_tele_def} ambient temperature=Ambient.*Temp pcie temperature=PCIE.*Temp
62 Verify Basic Telemetry Report Creation For PCIE
63 [Documentation] Verify basic telemetry report creations for PCIE.
/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_sensor.robot29 IPMI PCIE PCIE
39 DCMI PCIE PCIE
135 ${baseboard_temp_redfish}= Get Temperature Reading From Redfish PCIE
/openbmc/u-boot/board/toradex/apalis_t30/
H A Dpinmux-config-apalis_t30.h295 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
296 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
297 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
298 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
/openbmc/u-boot/board/freescale/t4qds/
H A DREADME107 0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
111 0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c313 NONE(PCIE),
/openbmc/u-boot/board/hisilicon/poplar/
H A DREADME18 PCIE One PCIe 2.0 interfaces

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