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Searched refs:PAD_CTL_PUS_100K_UP (Results 1 – 25 of 87) sorted by relevance

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/openbmc/u-boot/board/barco/platinum/
H A Dplatinum.h27 #define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \
31 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
34 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
37 #define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
41 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/openbmc/u-boot/board/tqc/tqma6/
H A Dtqma6_mba6.c32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
41 #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
44 #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
47 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
50 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
71 #define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
72 #define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
74 #define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
H A Dtqma6.c39 #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
42 #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
45 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
H A Dtqma6_wru4.c38 PAD_CTL_PUS_100K_UP | \
140 PAD_CTL_PUS_100K_UP | \
191 PAD_CTL_PUS_100K_UP | \
200 PAD_CTL_PUS_100K_UP | \
/openbmc/u-boot/board/gateworks/gw_ventana/
H A Dcommon.h19 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
34 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/openbmc/u-boot/board/liebherr/display5/
H A Dcommon.h11 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
31 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Diomux-mx25.h21 #define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
22 #define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
165 MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
173 MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
267 MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP),
342 MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
346 MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
412 MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
417 MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
422 MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
[all …]
/openbmc/u-boot/board/technexion/pico-imx6ul/
H A Dpico-imx6ul.c29 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
39 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/openbmc/u-boot/board/grinn/liteboard/
H A Dboard.c31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
38 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
42 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/openbmc/u-boot/board/phytec/pcl063/
H A Dpcl063.c32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
93 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
97 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/openbmc/u-boot/board/bachmann/ot1200/
H A Dot1200.c32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
45 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
113 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
/openbmc/u-boot/board/freescale/mx53ard/
H A Dmx53ard.c54 PAD_CTL_PUS_100K_UP), in setup_iomux_nand()
60 PAD_CTL_PUS_100K_UP), in setup_iomux_nand()
103 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
140 PAD_CTL_PUS_100K_UP)
/openbmc/u-boot/board/ccv/xpress/
H A Dxpress.c30 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
38 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
42 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
46 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dopos6ul.c24 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
29 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
39 PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
/openbmc/u-boot/board/toradex/colibri-imx6ull/
H A Dcolibri-imx6ull.c35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm)
49 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
/openbmc/u-boot/board/kosagi/novena/
H A Dnovena_spl.c31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
41 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
50 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
59 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
65 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/openbmc/u-boot/board/phytec/pcm058/
H A Dpcm058.c37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
57 #define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
60 #define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Diomux-v3.h142 #define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE) macro
203 #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) macro
222 #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) macro
/openbmc/u-boot/board/warp/
H A Dwarp.c31 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
42 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
/openbmc/u-boot/board/menlo/m53menlo/
H A Dm53menlo.c167 PAD_CTL_PUS_100K_UP)
353 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
394 PAD_CTL_PUS_100K_UP), in setup_iomux_nand()
396 PAD_CTL_PUS_100K_UP), in setup_iomux_nand()
/openbmc/u-boot/board/freescale/mx6sxsabreauto/
H A Dmx6sxsabreauto.c33 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
46 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
/openbmc/u-boot/board/aristainetos/
H A Daristainetos.c37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
51 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
/openbmc/u-boot/board/freescale/mx25pdk/
H A Dmx25pdk.c43 #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
95 #define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
/openbmc/u-boot/board/freescale/mx53smd/
H A Dmx53smd.c44 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
93 PAD_CTL_PUS_100K_UP)
/openbmc/u-boot/board/barco/titanium/
H A Dtitanium.c26 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
35 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \

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