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Searched refs:MSR_P4_TBPU_ESCR0 (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/x86/events/intel/
H A Dp4.c347 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR0 },
357 .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR1 },
1204 P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR0),
/openbmc/u-boot/arch/x86/include/asm/
H A Dmsr-index.h562 #define MSR_P4_TBPU_ESCR0 0x000003c2 macro
/openbmc/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h1033 #define MSR_P4_TBPU_ESCR0 0x000003c2 macro
/openbmc/linux/arch/x86/include/asm/
H A Dmsr-index.h1055 #define MSR_P4_TBPU_ESCR0 0x000003c2 macro