1444e2ff3SArnaldo Carvalho de Melo /* SPDX-License-Identifier: GPL-2.0 */ 2444e2ff3SArnaldo Carvalho de Melo #ifndef _ASM_X86_MSR_INDEX_H 3444e2ff3SArnaldo Carvalho de Melo #define _ASM_X86_MSR_INDEX_H 4444e2ff3SArnaldo Carvalho de Melo 5444e2ff3SArnaldo Carvalho de Melo #include <linux/bits.h> 6444e2ff3SArnaldo Carvalho de Melo 7a66558dcSArnaldo Carvalho de Melo /* CPU model specific register (MSR) numbers. */ 8444e2ff3SArnaldo Carvalho de Melo 9444e2ff3SArnaldo Carvalho de Melo /* x86-64 specific MSRs */ 10444e2ff3SArnaldo Carvalho de Melo #define MSR_EFER 0xc0000080 /* extended feature register */ 11444e2ff3SArnaldo Carvalho de Melo #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 12444e2ff3SArnaldo Carvalho de Melo #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 13444e2ff3SArnaldo Carvalho de Melo #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 14444e2ff3SArnaldo Carvalho de Melo #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 15444e2ff3SArnaldo Carvalho de Melo #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 16444e2ff3SArnaldo Carvalho de Melo #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 17444e2ff3SArnaldo Carvalho de Melo #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 18444e2ff3SArnaldo Carvalho de Melo #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 19444e2ff3SArnaldo Carvalho de Melo 20444e2ff3SArnaldo Carvalho de Melo /* EFER bits: */ 21444e2ff3SArnaldo Carvalho de Melo #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 22444e2ff3SArnaldo Carvalho de Melo #define _EFER_LME 8 /* Long mode enable */ 23444e2ff3SArnaldo Carvalho de Melo #define _EFER_LMA 10 /* Long mode active (read-only) */ 24444e2ff3SArnaldo Carvalho de Melo #define _EFER_NX 11 /* No execute enable */ 25444e2ff3SArnaldo Carvalho de Melo #define _EFER_SVME 12 /* Enable virtualization */ 26444e2ff3SArnaldo Carvalho de Melo #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 27444e2ff3SArnaldo Carvalho de Melo #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 283ee7cb4fSArnaldo Carvalho de Melo #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ 29444e2ff3SArnaldo Carvalho de Melo 30444e2ff3SArnaldo Carvalho de Melo #define EFER_SCE (1<<_EFER_SCE) 31444e2ff3SArnaldo Carvalho de Melo #define EFER_LME (1<<_EFER_LME) 32444e2ff3SArnaldo Carvalho de Melo #define EFER_LMA (1<<_EFER_LMA) 33444e2ff3SArnaldo Carvalho de Melo #define EFER_NX (1<<_EFER_NX) 34444e2ff3SArnaldo Carvalho de Melo #define EFER_SVME (1<<_EFER_SVME) 35444e2ff3SArnaldo Carvalho de Melo #define EFER_LMSLE (1<<_EFER_LMSLE) 36444e2ff3SArnaldo Carvalho de Melo #define EFER_FFXSR (1<<_EFER_FFXSR) 373ee7cb4fSArnaldo Carvalho de Melo #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) 38444e2ff3SArnaldo Carvalho de Melo 39444e2ff3SArnaldo Carvalho de Melo /* Intel MSRs. Some also available on other CPUs */ 40444e2ff3SArnaldo Carvalho de Melo 41bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL 0x00000033 42bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 43bab1a501SArnaldo Carvalho de Melo #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 44bab1a501SArnaldo Carvalho de Melo 45444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 46444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 47444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 48444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 49444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 50444e2ff3SArnaldo Carvalho de Melo #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 514ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ 524ad3278dSPawan Gupta #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) 53444e2ff3SArnaldo Carvalho de Melo 543ee7cb4fSArnaldo Carvalho de Melo /* A mask for bits which the kernel toggles when controlling mitigations */ 553ee7cb4fSArnaldo Carvalho de Melo #define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ 563ee7cb4fSArnaldo Carvalho de Melo | SPEC_CTRL_RRSBA_DIS_S) 573ee7cb4fSArnaldo Carvalho de Melo 58444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 59444e2ff3SArnaldo Carvalho de Melo #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 60*15ca3549SArnaldo Carvalho de Melo #define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */ 61444e2ff3SArnaldo Carvalho de Melo 62444e2ff3SArnaldo Carvalho de Melo #define MSR_PPIN_CTL 0x0000004e 63444e2ff3SArnaldo Carvalho de Melo #define MSR_PPIN 0x0000004f 64444e2ff3SArnaldo Carvalho de Melo 65444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERFCTR0 0x000000c1 66444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERFCTR1 0x000000c2 67444e2ff3SArnaldo Carvalho de Melo #define MSR_FSB_FREQ 0x000000cd 68444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO 0x000000ce 69444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 70444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 71444e2ff3SArnaldo Carvalho de Melo 72444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL 0xe1 73444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 74444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 75444e2ff3SArnaldo Carvalho de Melo /* 76444e2ff3SArnaldo Carvalho de Melo * The time field is bit[31:2], but representing a 32bit value with 77444e2ff3SArnaldo Carvalho de Melo * bit[1:0] zero. 78444e2ff3SArnaldo Carvalho de Melo */ 79444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 80444e2ff3SArnaldo Carvalho de Melo 81bab1a501SArnaldo Carvalho de Melo /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 82bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS 0x000000cf 839dde6cadSArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2 849dde6cadSArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT) 85bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 86bab1a501SArnaldo Carvalho de Melo #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 87bab1a501SArnaldo Carvalho de Melo 88444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 89444e2ff3SArnaldo Carvalho de Melo #define NHM_C3_AUTO_DEMOTE (1UL << 25) 90444e2ff3SArnaldo Carvalho de Melo #define NHM_C1_AUTO_DEMOTE (1UL << 26) 91444e2ff3SArnaldo Carvalho de Melo #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 92444e2ff3SArnaldo Carvalho de Melo #define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 93444e2ff3SArnaldo Carvalho de Melo #define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 94444e2ff3SArnaldo Carvalho de Melo 95444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRcap 0x000000fe 96444e2ff3SArnaldo Carvalho de Melo 97444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 98444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 99444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 10091d248c3SArnaldo Carvalho de Melo #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */ 101444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 102444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_SSB_NO BIT(4) /* 103444e2ff3SArnaldo Carvalho de Melo * Not susceptible to Speculative Store Bypass 104444e2ff3SArnaldo Carvalho de Melo * attack, so no Speculative Store Bypass 105444e2ff3SArnaldo Carvalho de Melo * control required. 106444e2ff3SArnaldo Carvalho de Melo */ 107444e2ff3SArnaldo Carvalho de Melo #define ARCH_CAP_MDS_NO BIT(5) /* 108444e2ff3SArnaldo Carvalho de Melo * Not susceptible to 109444e2ff3SArnaldo Carvalho de Melo * Microarchitectural Data 110444e2ff3SArnaldo Carvalho de Melo * Sampling (MDS) vulnerabilities. 111444e2ff3SArnaldo Carvalho de Melo */ 1128122b047SArnaldo Carvalho de Melo #define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 1138122b047SArnaldo Carvalho de Melo * The processor is not susceptible to a 1148122b047SArnaldo Carvalho de Melo * machine check error due to modifying the 1158122b047SArnaldo Carvalho de Melo * code page size along with either the 1168122b047SArnaldo Carvalho de Melo * physical address or cache type 1178122b047SArnaldo Carvalho de Melo * without TLB invalidation. 1188122b047SArnaldo Carvalho de Melo */ 1198122b047SArnaldo Carvalho de Melo #define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 1208122b047SArnaldo Carvalho de Melo #define ARCH_CAP_TAA_NO BIT(8) /* 1218122b047SArnaldo Carvalho de Melo * Not susceptible to 1228122b047SArnaldo Carvalho de Melo * TSX Async Abort (TAA) vulnerabilities. 1238122b047SArnaldo Carvalho de Melo */ 12451802186SPawan Gupta #define ARCH_CAP_SBDR_SSDP_NO BIT(13) /* 12551802186SPawan Gupta * Not susceptible to SBDR and SSDP 12651802186SPawan Gupta * variants of Processor MMIO stale data 12751802186SPawan Gupta * vulnerabilities. 12851802186SPawan Gupta */ 12951802186SPawan Gupta #define ARCH_CAP_FBSDP_NO BIT(14) /* 13051802186SPawan Gupta * Not susceptible to FBSDP variant of 13151802186SPawan Gupta * Processor MMIO stale data 13251802186SPawan Gupta * vulnerabilities. 13351802186SPawan Gupta */ 13451802186SPawan Gupta #define ARCH_CAP_PSDP_NO BIT(15) /* 13551802186SPawan Gupta * Not susceptible to PSDP variant of 13651802186SPawan Gupta * Processor MMIO stale data 13751802186SPawan Gupta * vulnerabilities. 13851802186SPawan Gupta */ 13951802186SPawan Gupta #define ARCH_CAP_FB_CLEAR BIT(17) /* 14051802186SPawan Gupta * VERW clears CPU fill buffer 14151802186SPawan Gupta * even on MDS_NO CPUs. 14251802186SPawan Gupta */ 143027bbb88SPawan Gupta #define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /* 144027bbb88SPawan Gupta * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] 145027bbb88SPawan Gupta * bit available to control VERW 146027bbb88SPawan Gupta * behavior. 147027bbb88SPawan Gupta */ 1484ad3278dSPawan Gupta #define ARCH_CAP_RRSBA BIT(19) /* 1494ad3278dSPawan Gupta * Indicates RET may use predictors 1504ad3278dSPawan Gupta * other than the RSB. With eIBRS 1514ad3278dSPawan Gupta * enabled predictions in kernel mode 1524ad3278dSPawan Gupta * are restricted to targets in 1534ad3278dSPawan Gupta * kernel. 1544ad3278dSPawan Gupta */ 1552b129932SDaniel Sneddon #define ARCH_CAP_PBRSB_NO BIT(24) /* 1562b129932SDaniel Sneddon * Not susceptible to Post-Barrier 1572b129932SDaniel Sneddon * Return Stack Buffer Predictions. 1582b129932SDaniel Sneddon */ 159*15ca3549SArnaldo Carvalho de Melo #define ARCH_CAP_GDS_CTRL BIT(25) /* 160*15ca3549SArnaldo Carvalho de Melo * CPU is vulnerable to Gather 161*15ca3549SArnaldo Carvalho de Melo * Data Sampling (GDS) and 162*15ca3549SArnaldo Carvalho de Melo * has controls for mitigation. 163*15ca3549SArnaldo Carvalho de Melo */ 164*15ca3549SArnaldo Carvalho de Melo #define ARCH_CAP_GDS_NO BIT(26) /* 165*15ca3549SArnaldo Carvalho de Melo * CPU is not vulnerable to Gather 166*15ca3549SArnaldo Carvalho de Melo * Data Sampling (GDS). 167*15ca3549SArnaldo Carvalho de Melo */ 168444e2ff3SArnaldo Carvalho de Melo 169a3a36565SArnaldo Carvalho de Melo #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* 170a3a36565SArnaldo Carvalho de Melo * IA32_XAPIC_DISABLE_STATUS MSR 171a3a36565SArnaldo Carvalho de Melo * supported 172a3a36565SArnaldo Carvalho de Melo */ 173a3a36565SArnaldo Carvalho de Melo 174444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_FLUSH_CMD 0x0000010b 175444e2ff3SArnaldo Carvalho de Melo #define L1D_FLUSH BIT(0) /* 176444e2ff3SArnaldo Carvalho de Melo * Writeback and invalidate the 177444e2ff3SArnaldo Carvalho de Melo * L1 data cache. 178444e2ff3SArnaldo Carvalho de Melo */ 179444e2ff3SArnaldo Carvalho de Melo 180444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BBL_CR_CTL 0x00000119 181444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BBL_CR_CTL3 0x0000011e 182444e2ff3SArnaldo Carvalho de Melo 1838122b047SArnaldo Carvalho de Melo #define MSR_IA32_TSX_CTRL 0x00000122 1848122b047SArnaldo Carvalho de Melo #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 1858122b047SArnaldo Carvalho de Melo #define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 1868122b047SArnaldo Carvalho de Melo 18725ca7e5cSArnaldo Carvalho de Melo #define MSR_IA32_MCU_OPT_CTRL 0x00000123 188400331f8SPawan Gupta #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */ 189400331f8SPawan Gupta #define RTM_ALLOW BIT(1) /* TSX development mode */ 190027bbb88SPawan Gupta #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ 191*15ca3549SArnaldo Carvalho de Melo #define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ 192*15ca3549SArnaldo Carvalho de Melo #define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ 19325ca7e5cSArnaldo Carvalho de Melo 194444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_CS 0x00000174 195444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_ESP 0x00000175 196444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SYSENTER_EIP 0x00000176 197444e2ff3SArnaldo Carvalho de Melo 198444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_CAP 0x00000179 199444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_STATUS 0x0000017a 200444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_CTL 0x0000017b 201e9bde94fSArnaldo Carvalho de Melo #define MSR_ERROR_CONTROL 0x0000017f 202444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EXT_CTL 0x000004d0 203444e2ff3SArnaldo Carvalho de Melo 204444e2ff3SArnaldo Carvalho de Melo #define MSR_OFFCORE_RSP_0 0x000001a6 205444e2ff3SArnaldo Carvalho de Melo #define MSR_OFFCORE_RSP_1 0x000001a7 206444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT 0x000001ad 207444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT1 0x000001ae 208444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_RATIO_LIMIT2 0x000001af 209444e2ff3SArnaldo Carvalho de Melo 2103ee7cb4fSArnaldo Carvalho de Melo #define MSR_SNOOP_RSP_0 0x00001328 2113ee7cb4fSArnaldo Carvalho de Melo #define MSR_SNOOP_RSP_1 0x00001329 2123ee7cb4fSArnaldo Carvalho de Melo 213444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_SELECT 0x000001c8 214444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_TOS 0x000001c9 215f815fe51SArnaldo Carvalho de Melo 216f815fe51SArnaldo Carvalho de Melo #define MSR_IA32_POWER_CTL 0x000001fc 217f815fe51SArnaldo Carvalho de Melo #define MSR_IA32_POWER_CTL_BIT_EE 19 218f815fe51SArnaldo Carvalho de Melo 2199dde6cadSArnaldo Carvalho de Melo /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ 2209dde6cadSArnaldo Carvalho de Melo #define MSR_INTEGRITY_CAPS 0x000002d9 22134e82891SYanteng Si #define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 22234e82891SYanteng Si #define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) 2239dde6cadSArnaldo Carvalho de Melo #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 2249dde6cadSArnaldo Carvalho de Melo #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) 2259dde6cadSArnaldo Carvalho de Melo 226444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_NHM_FROM 0x00000680 227444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_NHM_TO 0x000006c0 228444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_CORE_FROM 0x00000040 229444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_CORE_TO 0x00000060 230444e2ff3SArnaldo Carvalho de Melo 231444e2ff3SArnaldo Carvalho de Melo #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 232444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_MISPRED BIT_ULL(63) 233444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_IN_TX BIT_ULL(62) 234444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_ABORT BIT_ULL(61) 235f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 236444e2ff3SArnaldo Carvalho de Melo #define LBR_INFO_CYCLES 0xffff 237f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_BR_TYPE_OFFSET 56 238f815fe51SArnaldo Carvalho de Melo #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 239f815fe51SArnaldo Carvalho de Melo 240f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_CTL 0x000014ce 241f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_LBREN BIT(0) 242f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_CPL_OFFSET 1 243f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 244f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_STACK_OFFSET 3 245f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 246f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_FILTER_OFFSET 16 247f815fe51SArnaldo Carvalho de Melo #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 248f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_DEPTH 0x000014cf 249f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_FROM_0 0x00001500 250f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_TO_0 0x00001600 251f815fe51SArnaldo Carvalho de Melo #define MSR_ARCH_LBR_INFO_0 0x00001200 252444e2ff3SArnaldo Carvalho de Melo 253444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PEBS_ENABLE 0x000003f1 254444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_DATA_CFG 0x000003f2 255444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_DS_AREA 0x00000600 256444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_CAPABILITIES 0x00000345 257b3172585SArnaldo Carvalho de Melo #define PERF_CAP_METRICS_IDX 15 258b3172585SArnaldo Carvalho de Melo #define PERF_CAP_PT_IDX 16 259b3172585SArnaldo Carvalho de Melo 260444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 2617f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_PEBS_TRAP BIT_ULL(6) 2627f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_ARCH_REG BIT_ULL(7) 2637f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_PEBS_FORMAT 0xf00 2647f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) 2657f7f86a7SArnaldo Carvalho de Melo #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ 2667f7f86a7SArnaldo Carvalho de Melo PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE) 267444e2ff3SArnaldo Carvalho de Melo 268444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_CTL 0x00000570 269444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TRACEEN BIT(0) 270444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYCLEACC BIT(1) 271444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_OS BIT(2) 272444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_USR BIT(3) 273444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PWR_EVT_EN BIT(4) 274444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_FUP_ON_PTW BIT(5) 275444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_FABRIC_EN BIT(6) 276444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CR3EN BIT(7) 277444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TOPA BIT(8) 278444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_EN BIT(9) 279444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_TSC_EN BIT(10) 280444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_DISRETC BIT(11) 281444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PTW_EN BIT(12) 282444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_BRANCH_EN BIT(13) 283672b259fSArnaldo Carvalho de Melo #define RTIT_CTL_EVENT_EN BIT(31) 284672b259fSArnaldo Carvalho de Melo #define RTIT_CTL_NOTNT BIT_ULL(55) 285444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_RANGE_OFFSET 14 286444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 287444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYC_THRESH_OFFSET 19 288444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 289444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PSB_FREQ_OFFSET 24 290444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 291444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR0_OFFSET 32 292444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 293444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR1_OFFSET 36 294444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 295444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR2_OFFSET 40 296444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 297444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR3_OFFSET 44 298444e2ff3SArnaldo Carvalho de Melo #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 299444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_STATUS 0x00000571 300444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_FILTEREN BIT(0) 301444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_CONTEXTEN BIT(1) 302444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_TRIGGEREN BIT(2) 303444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BUFFOVF BIT(3) 304444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_ERROR BIT(4) 305444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_STOPPED BIT(5) 306444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BYTECNT_OFFSET 32 307444e2ff3SArnaldo Carvalho de Melo #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 308444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR0_A 0x00000580 309444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR0_B 0x00000581 310444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR1_A 0x00000582 311444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR1_B 0x00000583 312444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR2_A 0x00000584 313444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR2_B 0x00000585 314444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR3_A 0x00000586 315444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_ADDR3_B 0x00000587 316444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 317444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 318444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 319444e2ff3SArnaldo Carvalho de Melo 320444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix64K_00000 0x00000250 321444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix16K_80000 0x00000258 322444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix16K_A0000 0x00000259 323444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_C0000 0x00000268 324444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_C8000 0x00000269 325444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_D0000 0x0000026a 326444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_D8000 0x0000026b 327444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_E0000 0x0000026c 328444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_E8000 0x0000026d 329444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_F0000 0x0000026e 330444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRfix4K_F8000 0x0000026f 331444e2ff3SArnaldo Carvalho de Melo #define MSR_MTRRdefType 0x000002ff 332444e2ff3SArnaldo Carvalho de Melo 333444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_CR_PAT 0x00000277 334444e2ff3SArnaldo Carvalho de Melo 335444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_DEBUGCTLMSR 0x000001d9 336444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 337444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 338444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTINTFROMIP 0x000001dd 339444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_LASTINTTOIP 0x000001de 340444e2ff3SArnaldo Carvalho de Melo 34132b734e0SArnaldo Carvalho de Melo #define MSR_IA32_PASID 0x00000d93 34232b734e0SArnaldo Carvalho de Melo #define MSR_IA32_PASID_VALID BIT_ULL(31) 34332b734e0SArnaldo Carvalho de Melo 344444e2ff3SArnaldo Carvalho de Melo /* DEBUGCTLMSR bits (others vary by model): */ 345444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 346444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTF_SHIFT 1 347444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 348b3172585SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 349444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_TR (1UL << 6) 350444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS (1UL << 7) 351444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTINT (1UL << 8) 352444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 353444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 354444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 355444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 356444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 357444e2ff3SArnaldo Carvalho de Melo #define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 358444e2ff3SArnaldo Carvalho de Melo 359444e2ff3SArnaldo Carvalho de Melo #define MSR_PEBS_FRONTEND 0x000003f7 360444e2ff3SArnaldo Carvalho de Melo 361444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_CTL 0x00000400 362444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_STATUS 0x00000401 363444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_ADDR 0x00000402 364444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_MISC 0x00000403 365444e2ff3SArnaldo Carvalho de Melo 366444e2ff3SArnaldo Carvalho de Melo /* C-state Residency Counters */ 367444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C3_RESIDENCY 0x000003f8 368444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C6_RESIDENCY 0x000003f9 369444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 370444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C7_RESIDENCY 0x000003fa 371444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C3_RESIDENCY 0x000003fc 372444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C6_RESIDENCY 0x000003fd 373444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C7_RESIDENCY 0x000003fe 374444e2ff3SArnaldo Carvalho de Melo #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 375444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C2_RESIDENCY 0x0000060d 376444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C8_RESIDENCY 0x00000630 377444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C9_RESIDENCY 0x00000631 378444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_C10_RESIDENCY 0x00000632 379444e2ff3SArnaldo Carvalho de Melo 380444e2ff3SArnaldo Carvalho de Melo /* Interrupt Response Limit */ 381444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC3_IRTL 0x0000060a 382444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC6_IRTL 0x0000060b 383444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC7_IRTL 0x0000060c 384444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC8_IRTL 0x00000633 385444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC9_IRTL 0x00000634 386444e2ff3SArnaldo Carvalho de Melo #define MSR_PKGC10_IRTL 0x00000635 387444e2ff3SArnaldo Carvalho de Melo 388444e2ff3SArnaldo Carvalho de Melo /* Run Time Average Power Limiting (RAPL) Interface */ 389444e2ff3SArnaldo Carvalho de Melo 3909dde6cadSArnaldo Carvalho de Melo #define MSR_VR_CURRENT_CONFIG 0x00000601 391444e2ff3SArnaldo Carvalho de Melo #define MSR_RAPL_POWER_UNIT 0x00000606 392444e2ff3SArnaldo Carvalho de Melo 393444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_POWER_LIMIT 0x00000610 394444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ENERGY_STATUS 0x00000611 395444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_PERF_STATUS 0x00000613 396444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_POWER_INFO 0x00000614 397444e2ff3SArnaldo Carvalho de Melo 398444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_POWER_LIMIT 0x00000618 399444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_ENERGY_STATUS 0x00000619 400444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_PERF_STATUS 0x0000061b 401444e2ff3SArnaldo Carvalho de Melo #define MSR_DRAM_POWER_INFO 0x0000061c 402444e2ff3SArnaldo Carvalho de Melo 403444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_POWER_LIMIT 0x00000638 404444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_ENERGY_STATUS 0x00000639 405444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_POLICY 0x0000063a 406444e2ff3SArnaldo Carvalho de Melo #define MSR_PP0_PERF_STATUS 0x0000063b 407444e2ff3SArnaldo Carvalho de Melo 408444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_POWER_LIMIT 0x00000640 409444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_ENERGY_STATUS 0x00000641 410444e2ff3SArnaldo Carvalho de Melo #define MSR_PP1_POLICY 0x00000642 411444e2ff3SArnaldo Carvalho de Melo 4123b1f47d6SArnaldo Carvalho de Melo #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 413e9bde94fSArnaldo Carvalho de Melo #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 414e9bde94fSArnaldo Carvalho de Melo #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 4153b1f47d6SArnaldo Carvalho de Melo 416444e2ff3SArnaldo Carvalho de Melo /* Config TDP MSRs */ 417444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_NOMINAL 0x00000648 418444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_LEVEL_1 0x00000649 419444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 420444e2ff3SArnaldo Carvalho de Melo #define MSR_CONFIG_TDP_CONTROL 0x0000064B 421444e2ff3SArnaldo Carvalho de Melo #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 422444e2ff3SArnaldo Carvalho de Melo 423444e2ff3SArnaldo Carvalho de Melo #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 4247f7f86a7SArnaldo Carvalho de Melo #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650 425444e2ff3SArnaldo Carvalho de Melo 426444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 427444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 428444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 429444e2ff3SArnaldo Carvalho de Melo #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 430444e2ff3SArnaldo Carvalho de Melo 431444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_C1_RES 0x00000660 432444e2ff3SArnaldo Carvalho de Melo #define MSR_MODULE_C6_RES_MS 0x00000664 433444e2ff3SArnaldo Carvalho de Melo 434444e2ff3SArnaldo Carvalho de Melo #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 435444e2ff3SArnaldo Carvalho de Melo #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 436444e2ff3SArnaldo Carvalho de Melo 437444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_RATIOS 0x0000066a 438444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_VIDS 0x0000066b 439444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 440444e2ff3SArnaldo Carvalho de Melo #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 441444e2ff3SArnaldo Carvalho de Melo 442444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 443444e2ff3SArnaldo Carvalho de Melo #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 444444e2ff3SArnaldo Carvalho de Melo #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 445444e2ff3SArnaldo Carvalho de Melo 446672b259fSArnaldo Carvalho de Melo /* Control-flow Enforcement Technology MSRs */ 447672b259fSArnaldo Carvalho de Melo #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ 448672b259fSArnaldo Carvalho de Melo #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ 449672b259fSArnaldo Carvalho de Melo #define CET_SHSTK_EN BIT_ULL(0) 450672b259fSArnaldo Carvalho de Melo #define CET_WRSS_EN BIT_ULL(1) 451672b259fSArnaldo Carvalho de Melo #define CET_ENDBR_EN BIT_ULL(2) 452672b259fSArnaldo Carvalho de Melo #define CET_LEG_IW_EN BIT_ULL(3) 453672b259fSArnaldo Carvalho de Melo #define CET_NO_TRACK_EN BIT_ULL(4) 454672b259fSArnaldo Carvalho de Melo #define CET_SUPPRESS_DISABLE BIT_ULL(5) 455672b259fSArnaldo Carvalho de Melo #define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) 456672b259fSArnaldo Carvalho de Melo #define CET_SUPPRESS BIT_ULL(10) 457672b259fSArnaldo Carvalho de Melo #define CET_WAIT_ENDBR BIT_ULL(11) 458672b259fSArnaldo Carvalho de Melo 459672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ 460672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ 461672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ 462672b259fSArnaldo Carvalho de Melo #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ 463672b259fSArnaldo Carvalho de Melo #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ 464672b259fSArnaldo Carvalho de Melo 465444e2ff3SArnaldo Carvalho de Melo /* Hardware P state interface */ 466444e2ff3SArnaldo Carvalho de Melo #define MSR_PPERF 0x0000064e 467444e2ff3SArnaldo Carvalho de Melo #define MSR_PERF_LIMIT_REASONS 0x0000064f 468444e2ff3SArnaldo Carvalho de Melo #define MSR_PM_ENABLE 0x00000770 469444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_CAPABILITIES 0x00000771 470444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_REQUEST_PKG 0x00000772 471444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_INTERRUPT 0x00000773 472444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_REQUEST 0x00000774 473444e2ff3SArnaldo Carvalho de Melo #define MSR_HWP_STATUS 0x00000777 474444e2ff3SArnaldo Carvalho de Melo 475444e2ff3SArnaldo Carvalho de Melo /* CPUID.6.EAX */ 476444e2ff3SArnaldo Carvalho de Melo #define HWP_BASE_BIT (1<<7) 477444e2ff3SArnaldo Carvalho de Melo #define HWP_NOTIFICATIONS_BIT (1<<8) 478444e2ff3SArnaldo Carvalho de Melo #define HWP_ACTIVITY_WINDOW_BIT (1<<9) 479444e2ff3SArnaldo Carvalho de Melo #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 480444e2ff3SArnaldo Carvalho de Melo #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 481444e2ff3SArnaldo Carvalho de Melo 482444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_CAPABILITIES */ 483444e2ff3SArnaldo Carvalho de Melo #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 484444e2ff3SArnaldo Carvalho de Melo #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 485444e2ff3SArnaldo Carvalho de Melo #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 486444e2ff3SArnaldo Carvalho de Melo #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 487444e2ff3SArnaldo Carvalho de Melo 488444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_REQUEST */ 489444e2ff3SArnaldo Carvalho de Melo #define HWP_MIN_PERF(x) (x & 0xff) 490444e2ff3SArnaldo Carvalho de Melo #define HWP_MAX_PERF(x) ((x & 0xff) << 8) 491444e2ff3SArnaldo Carvalho de Melo #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 492444e2ff3SArnaldo Carvalho de Melo #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 493444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_PERFORMANCE 0x00 494444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_BALANCE_PERFORMANCE 0x80 495444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_BALANCE_POWERSAVE 0xC0 496444e2ff3SArnaldo Carvalho de Melo #define HWP_EPP_POWERSAVE 0xFF 497444e2ff3SArnaldo Carvalho de Melo #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 498444e2ff3SArnaldo Carvalho de Melo #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 499444e2ff3SArnaldo Carvalho de Melo 500444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_STATUS */ 501444e2ff3SArnaldo Carvalho de Melo #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 502444e2ff3SArnaldo Carvalho de Melo #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 503444e2ff3SArnaldo Carvalho de Melo 504444e2ff3SArnaldo Carvalho de Melo /* IA32_HWP_INTERRUPT */ 505444e2ff3SArnaldo Carvalho de Melo #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 506444e2ff3SArnaldo Carvalho de Melo #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 507444e2ff3SArnaldo Carvalho de Melo 508444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_MC0_MASK 0xc0010044 509444e2ff3SArnaldo Carvalho de Melo 510444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 511444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 512444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 513444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 514444e2ff3SArnaldo Carvalho de Melo 515444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 516444e2ff3SArnaldo Carvalho de Melo 517444e2ff3SArnaldo Carvalho de Melo /* These are consecutive and not in the normal 4er MCE bank block */ 518444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MC0_CTL2 0x00000280 519444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 520444e2ff3SArnaldo Carvalho de Melo 521444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_PERFCTR0 0x000000c1 522444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_PERFCTR1 0x000000c2 523444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_EVNTSEL0 0x00000186 524444e2ff3SArnaldo Carvalho de Melo #define MSR_P6_EVNTSEL1 0x00000187 525444e2ff3SArnaldo Carvalho de Melo 526444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_PERFCTR0 0x00000020 527444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_PERFCTR1 0x00000021 528444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_EVNTSEL0 0x00000028 529444e2ff3SArnaldo Carvalho de Melo #define MSR_KNC_EVNTSEL1 0x00000029 530444e2ff3SArnaldo Carvalho de Melo 531444e2ff3SArnaldo Carvalho de Melo /* Alternative perfctr range with full access. */ 532444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PMC0 0x000004c1 533444e2ff3SArnaldo Carvalho de Melo 534444e2ff3SArnaldo Carvalho de Melo /* Auto-reload via MSR instead of DS area */ 535444e2ff3SArnaldo Carvalho de Melo #define MSR_RELOAD_PMC0 0x000014c1 536444e2ff3SArnaldo Carvalho de Melo #define MSR_RELOAD_FIXED_CTR0 0x00001309 537444e2ff3SArnaldo Carvalho de Melo 538444e2ff3SArnaldo Carvalho de Melo /* 539444e2ff3SArnaldo Carvalho de Melo * AMD64 MSRs. Not complete. See the architecture manual for a more 540444e2ff3SArnaldo Carvalho de Melo * complete list. 541444e2ff3SArnaldo Carvalho de Melo */ 542444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_PATCH_LEVEL 0x0000008b 543444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_TSC_RATIO 0xc0000104 544444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_NB_CFG 0xc001001f 545444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_PATCH_LOADER 0xc0010020 546444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PERF_CTL 0xc0010062 547444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PERF_STATUS 0xc0010063 548444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 549444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 550444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_OSVW_STATUS 0xc0010141 5518122b047SArnaldo Carvalho de Melo #define MSR_AMD_PPIN_CTL 0xc00102f0 5528122b047SArnaldo Carvalho de Melo #define MSR_AMD_PPIN 0xc00102f1 553f815fe51SArnaldo Carvalho de Melo #define MSR_AMD64_CPUID_FN_1 0xc0011004 554444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_LS_CFG 0xc0011020 555444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_DC_CFG 0xc0011022 5562632daebSBorislav Petkov 5572632daebSBorislav Petkov #define MSR_AMD64_DE_CFG 0xc0011029 5582632daebSBorislav Petkov #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 5592632daebSBorislav Petkov #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) 5608cdd4aefSArnaldo Carvalho de Melo #define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 5612632daebSBorislav Petkov 562444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_BU_CFG2 0xc001102a 563444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHCTL 0xc0011030 564444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 565444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 566444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCH_REG_COUNT 3 567444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 568444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPCTL 0xc0011033 569444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPRIP 0xc0011034 570444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA 0xc0011035 571444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA2 0xc0011036 572444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA3 0xc0011037 573444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSDCLINAD 0xc0011038 574444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 575444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOP_REG_COUNT 7 576444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 577444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSCTL 0xc001103a 578444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSBRTARGET 0xc001103b 57932b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 580444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBSOPDATA4 0xc001103d 581444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 5825b061a32SArnaldo Carvalho de Melo #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b 583fde66824SArnaldo Carvalho de Melo #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 58432b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 585444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV 0xc0010131 586444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ENABLED_BIT 0 58732b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 5889dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 589444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 59032b734e0SArnaldo Carvalho de Melo #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 5919dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) 592444e2ff3SArnaldo Carvalho de Melo 5933ef9fec0SArnaldo Carvalho de Melo /* SNP feature bits enabled by the hypervisor */ 5943ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_VTOM BIT_ULL(3) 5953ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4) 5963ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5) 5973ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6) 5983ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7) 5993ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8) 6003ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9) 6013ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10) 6023ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11) 6033ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12) 6043ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14) 6053ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16) 6063ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17) 6073ef9fec0SArnaldo Carvalho de Melo 6083ef9fec0SArnaldo Carvalho de Melo /* SNP feature bits reserved for future use. */ 6093ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13) 6103ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15) 6113ef9fec0SArnaldo Carvalho de Melo #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18) 6123ef9fec0SArnaldo Carvalho de Melo 613444e2ff3SArnaldo Carvalho de Melo #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 614444e2ff3SArnaldo Carvalho de Melo 615e652ab64SArnaldo Carvalho de Melo /* AMD Collaborative Processor Performance Control MSRs */ 616e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_CAP1 0xc00102b0 617e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_ENABLE 0xc00102b1 618e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_CAP2 0xc00102b2 619e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_REQ 0xc00102b3 620e652ab64SArnaldo Carvalho de Melo #define MSR_AMD_CPPC_STATUS 0xc00102b4 621e652ab64SArnaldo Carvalho de Melo 622e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) 623e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) 624e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) 625e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) 626e652ab64SArnaldo Carvalho de Melo 627e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) 628e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) 629e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) 630e652ab64SArnaldo Carvalho de Melo #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) 631e652ab64SArnaldo Carvalho de Melo 6329dde6cadSArnaldo Carvalho de Melo /* AMD Performance Counter Global Status and Control MSRs */ 6339dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 6349dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 6359dde6cadSArnaldo Carvalho de Melo #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 6369dde6cadSArnaldo Carvalho de Melo 637a3a36565SArnaldo Carvalho de Melo /* AMD Last Branch Record MSRs */ 638a3a36565SArnaldo Carvalho de Melo #define MSR_AMD64_LBR_SELECT 0xc000010e 639a3a36565SArnaldo Carvalho de Melo 640444e2ff3SArnaldo Carvalho de Melo /* Fam 17h MSRs */ 641444e2ff3SArnaldo Carvalho de Melo #define MSR_F17H_IRPERF 0xc00000e9 642444e2ff3SArnaldo Carvalho de Melo 64391d248c3SArnaldo Carvalho de Melo #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3 64491d248c3SArnaldo Carvalho de Melo #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1) 64591d248c3SArnaldo Carvalho de Melo 646444e2ff3SArnaldo Carvalho de Melo /* Fam 16h MSRs */ 647444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_L2I_PERF_CTL 0xc0010230 648444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_L2I_PERF_CTR 0xc0010231 649444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 650444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR2_ADDR_MASK 0xc001101a 651444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR3_ADDR_MASK 0xc001101b 652444e2ff3SArnaldo Carvalho de Melo #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 653444e2ff3SArnaldo Carvalho de Melo 654444e2ff3SArnaldo Carvalho de Melo /* Fam 15h MSRs */ 655f815fe51SArnaldo Carvalho de Melo #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 656f815fe51SArnaldo Carvalho de Melo #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 657444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL 0xc0010200 658444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 659444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 660444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 661444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 662444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 663444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 664444e2ff3SArnaldo Carvalho de Melo 665444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR 0xc0010201 666444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 667444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 668444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 669444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 670444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 671444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 672444e2ff3SArnaldo Carvalho de Melo 673444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_NB_PERF_CTL 0xc0010240 674444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_NB_PERF_CTR 0xc0010241 675444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_PTSC 0xc0010280 676444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_IC_CFG 0xc0011021 677444e2ff3SArnaldo Carvalho de Melo #define MSR_F15H_EX_CFG 0xc001102c 678444e2ff3SArnaldo Carvalho de Melo 679444e2ff3SArnaldo Carvalho de Melo /* Fam 10h MSRs */ 680444e2ff3SArnaldo Carvalho de Melo #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 681444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_ENABLE (1<<0) 682444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 683444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 684444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 685444e2ff3SArnaldo Carvalho de Melo #define FAM10H_MMIO_CONF_BASE_SHIFT 20 686444e2ff3SArnaldo Carvalho de Melo #define MSR_FAM10H_NODE_ID 0xc001100c 687444e2ff3SArnaldo Carvalho de Melo 688444e2ff3SArnaldo Carvalho de Melo /* K8 MSRs */ 689444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TOP_MEM1 0xc001001a 690444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TOP_MEM2 0xc001001d 691059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG 0xc0010010 692059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 693059e5c32SBrijesh Singh #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 694444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_INT_PENDING_MSG 0xc0010055 695444e2ff3SArnaldo Carvalho de Melo /* C1E active bits in int pending message */ 696444e2ff3SArnaldo Carvalho de Melo #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 697444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TSEG_ADDR 0xc0010112 698444e2ff3SArnaldo Carvalho de Melo #define MSR_K8_TSEG_MASK 0xc0010113 699444e2ff3SArnaldo Carvalho de Melo #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 700444e2ff3SArnaldo Carvalho de Melo #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 701444e2ff3SArnaldo Carvalho de Melo #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 702444e2ff3SArnaldo Carvalho de Melo 703444e2ff3SArnaldo Carvalho de Melo /* K7 MSRs */ 704444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL0 0xc0010000 705444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR0 0xc0010004 706444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL1 0xc0010001 707444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR1 0xc0010005 708444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL2 0xc0010002 709444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR2 0xc0010006 710444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_EVNTSEL3 0xc0010003 711444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_PERFCTR3 0xc0010007 712444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_CLK_CTL 0xc001001b 713444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR 0xc0010015 714444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR_SMMLOCK_BIT 0 715444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 716d8e3ee2eSArnaldo Carvalho de Melo #define MSR_K7_HWCR_IRPERF_EN_BIT 30 717d8e3ee2eSArnaldo Carvalho de Melo #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 718444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_FID_VID_CTL 0xc0010041 719444e2ff3SArnaldo Carvalho de Melo #define MSR_K7_FID_VID_STATUS 0xc0010042 720444e2ff3SArnaldo Carvalho de Melo 721444e2ff3SArnaldo Carvalho de Melo /* K6 MSRs */ 722444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_WHCR 0xc0000082 723444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_UWCCR 0xc0000085 724444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_EPMR 0xc0000086 725444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_PSOR 0xc0000087 726444e2ff3SArnaldo Carvalho de Melo #define MSR_K6_PFIR 0xc0000088 727444e2ff3SArnaldo Carvalho de Melo 728444e2ff3SArnaldo Carvalho de Melo /* Centaur-Hauls/IDT defined MSRs. */ 729444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR1 0x00000107 730444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR2 0x00000108 731444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR3 0x00000109 732444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_FCR4 0x0000010a 733444e2ff3SArnaldo Carvalho de Melo 734444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR0 0x00000110 735444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR1 0x00000111 736444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR2 0x00000112 737444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR3 0x00000113 738444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR4 0x00000114 739444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR5 0x00000115 740444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR6 0x00000116 741444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR7 0x00000117 742444e2ff3SArnaldo Carvalho de Melo #define MSR_IDT_MCR_CTRL 0x00000120 743444e2ff3SArnaldo Carvalho de Melo 744444e2ff3SArnaldo Carvalho de Melo /* VIA Cyrix defined MSRs*/ 745444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_FCR 0x00001107 746444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_LONGHAUL 0x0000110a 747444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_RNG 0x0000110b 748444e2ff3SArnaldo Carvalho de Melo #define MSR_VIA_BCR2 0x00001147 749444e2ff3SArnaldo Carvalho de Melo 750444e2ff3SArnaldo Carvalho de Melo /* Transmeta defined MSRs */ 751444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LONGRUN_CTRL 0x80868010 752444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 753444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LRTI_READOUT 0x80868018 754444e2ff3SArnaldo Carvalho de Melo #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 755444e2ff3SArnaldo Carvalho de Melo 756444e2ff3SArnaldo Carvalho de Melo /* Intel defined MSRs. */ 757444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_P5_MC_ADDR 0x00000000 758444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_P5_MC_TYPE 0x00000001 759444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC 0x00000010 760444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PLATFORM_ID 0x00000017 761444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_EBL_CR_POWERON 0x0000002a 762444e2ff3SArnaldo Carvalho de Melo #define MSR_EBC_FREQUENCY_ID 0x0000002c 763444e2ff3SArnaldo Carvalho de Melo #define MSR_SMI_COUNT 0x00000034 764f6505c88SSean Christopherson 765f6505c88SSean Christopherson /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 766f6505c88SSean Christopherson #define MSR_IA32_FEAT_CTL 0x0000003a 767f6505c88SSean Christopherson #define FEAT_CTL_LOCKED BIT(0) 768f6505c88SSean Christopherson #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 769f6505c88SSean Christopherson #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 770e9bde94fSArnaldo Carvalho de Melo #define FEAT_CTL_SGX_LC_ENABLED BIT(17) 771e9bde94fSArnaldo Carvalho de Melo #define FEAT_CTL_SGX_ENABLED BIT(18) 772f6505c88SSean Christopherson #define FEAT_CTL_LMCE_ENABLED BIT(20) 773f6505c88SSean Christopherson 774444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC_ADJUST 0x0000003b 775444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BNDCFGS 0x00000d90 776444e2ff3SArnaldo Carvalho de Melo 777444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 778444e2ff3SArnaldo Carvalho de Melo 7793442b5e0SArnaldo Carvalho de Melo #define MSR_IA32_XFD 0x000001c4 7803442b5e0SArnaldo Carvalho de Melo #define MSR_IA32_XFD_ERR 0x000001c5 781444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_XSS 0x00000da0 782444e2ff3SArnaldo Carvalho de Melo 783444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE 0x0000001b 784444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_BSP (1<<8) 785444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_ENABLE (1<<11) 786444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 787444e2ff3SArnaldo Carvalho de Melo 788444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UCODE_WRITE 0x00000079 789444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_UCODE_REV 0x0000008b 790444e2ff3SArnaldo Carvalho de Melo 791e9bde94fSArnaldo Carvalho de Melo /* Intel SGX Launch Enclave Public Key Hash MSRs */ 792e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 793e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 794e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 795e9bde94fSArnaldo Carvalho de Melo #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 796e9bde94fSArnaldo Carvalho de Melo 797444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 798444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_SMBASE 0x0000009e 799444e2ff3SArnaldo Carvalho de Melo 800444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_STATUS 0x00000198 801444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PERF_CTL 0x00000199 802444e2ff3SArnaldo Carvalho de Melo #define INTEL_PERF_CTL_MASK 0xffff 803444e2ff3SArnaldo Carvalho de Melo 8049dde6cadSArnaldo Carvalho de Melo /* AMD Branch Sampling configuration */ 8059dde6cadSArnaldo Carvalho de Melo #define MSR_AMD_DBG_EXTN_CFG 0xc000010f 8069dde6cadSArnaldo Carvalho de Melo #define MSR_AMD_SAMP_BR_FROM 0xc0010300 8079dde6cadSArnaldo Carvalho de Melo 808a3a36565SArnaldo Carvalho de Melo #define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6) 809a3a36565SArnaldo Carvalho de Melo 810444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MPERF 0x000000e7 811444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_APERF 0x000000e8 812444e2ff3SArnaldo Carvalho de Melo 813444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_CONTROL 0x0000019a 814444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_INTERRUPT 0x0000019b 815444e2ff3SArnaldo Carvalho de Melo 816444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_HIGH_ENABLE (1 << 0) 817444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_LOW_ENABLE (1 << 1) 818444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_PLN_ENABLE (1 << 24) 819444e2ff3SArnaldo Carvalho de Melo 820444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_THERM_STATUS 0x0000019c 821444e2ff3SArnaldo Carvalho de Melo 822444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_PROCHOT (1 << 0) 823444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_POWER_LIMIT (1 << 10) 824444e2ff3SArnaldo Carvalho de Melo 825444e2ff3SArnaldo Carvalho de Melo #define MSR_THERM2_CTL 0x0000019d 826444e2ff3SArnaldo Carvalho de Melo 827444e2ff3SArnaldo Carvalho de Melo #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 828444e2ff3SArnaldo Carvalho de Melo 829444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE 0x000001a0 830444e2ff3SArnaldo Carvalho de Melo 831444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 832444e2ff3SArnaldo Carvalho de Melo 833444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURE_CONTROL 0x000001a4 834444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_PWR_MGMT 0x000001aa 835444e2ff3SArnaldo Carvalho de Melo 836444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 837444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_PERFORMANCE 0 838444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 839444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_NORMAL 6 840a66558dcSArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7 841444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 842444e2ff3SArnaldo Carvalho de Melo #define ENERGY_PERF_BIAS_POWERSAVE 15 843444e2ff3SArnaldo Carvalho de Melo 844444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 845444e2ff3SArnaldo Carvalho de Melo 846444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 847444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 84861726144SArnaldo Carvalho de Melo #define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) 849444e2ff3SArnaldo Carvalho de Melo 850444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 851444e2ff3SArnaldo Carvalho de Melo 852444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 853444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 854444e2ff3SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 85561726144SArnaldo Carvalho de Melo #define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) 856444e2ff3SArnaldo Carvalho de Melo 857444e2ff3SArnaldo Carvalho de Melo /* Thermal Thresholds Support */ 858444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 859444e2ff3SArnaldo Carvalho de Melo #define THERM_SHIFT_THRESHOLD0 8 860444e2ff3SArnaldo Carvalho de Melo #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 861444e2ff3SArnaldo Carvalho de Melo #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 862444e2ff3SArnaldo Carvalho de Melo #define THERM_SHIFT_THRESHOLD1 16 863444e2ff3SArnaldo Carvalho de Melo #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 864444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_THRESHOLD0 (1 << 6) 865444e2ff3SArnaldo Carvalho de Melo #define THERM_LOG_THRESHOLD0 (1 << 7) 866444e2ff3SArnaldo Carvalho de Melo #define THERM_STATUS_THRESHOLD1 (1 << 8) 867444e2ff3SArnaldo Carvalho de Melo #define THERM_LOG_THRESHOLD1 (1 << 9) 868444e2ff3SArnaldo Carvalho de Melo 869444e2ff3SArnaldo Carvalho de Melo /* MISC_ENABLE bits: architectural */ 870444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 871444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 872444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 873444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 874444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 875444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 876444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 877444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 878444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 879444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 880444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 881444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 882444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 883444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 884444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 885444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 886444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 887444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 888444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 889444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 890444e2ff3SArnaldo Carvalho de Melo 891444e2ff3SArnaldo Carvalho de Melo /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 892444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 893444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 894444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 895444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 896444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 897444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 898444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 899444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 900444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 901444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 902444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 903444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 904444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 905444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 906444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 907444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 908444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 909444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 910444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 911444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 912444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 913444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 914444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 915444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 916444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 917444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 918444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 919444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 920444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 921444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 922444e2ff3SArnaldo Carvalho de Melo 923444e2ff3SArnaldo Carvalho de Melo /* MISC_FEATURES_ENABLES non-architectural features */ 924444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES 0x00000140 925444e2ff3SArnaldo Carvalho de Melo 926444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 927444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 928444e2ff3SArnaldo Carvalho de Melo #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 929444e2ff3SArnaldo Carvalho de Melo 930444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_TSC_DEADLINE 0x000006E0 931444e2ff3SArnaldo Carvalho de Melo 932444e2ff3SArnaldo Carvalho de Melo 933444e2ff3SArnaldo Carvalho de Melo #define MSR_TSX_FORCE_ABORT 0x0000010F 934444e2ff3SArnaldo Carvalho de Melo 935444e2ff3SArnaldo Carvalho de Melo #define MSR_TFA_RTM_FORCE_ABORT_BIT 0 936444e2ff3SArnaldo Carvalho de Melo #define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 93704df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 93804df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 93904df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_SDV_ENABLE_RTM_BIT 2 94004df0dc1SArnaldo Carvalho de Melo #define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 941444e2ff3SArnaldo Carvalho de Melo 942444e2ff3SArnaldo Carvalho de Melo /* P4/Xeon+ specific */ 943444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EAX 0x00000180 944444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EBX 0x00000181 945444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ECX 0x00000182 946444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EDX 0x00000183 947444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ESI 0x00000184 948444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EDI 0x00000185 949444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EBP 0x00000186 950444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_ESP 0x00000187 951444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EFLAGS 0x00000188 952444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_EIP 0x00000189 953444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_MCG_RESERVED 0x0000018a 954444e2ff3SArnaldo Carvalho de Melo 955444e2ff3SArnaldo Carvalho de Melo /* Pentium IV performance counter MSRs */ 956444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR0 0x00000300 957444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR1 0x00000301 958444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR2 0x00000302 959444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_PERFCTR3 0x00000303 960444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR0 0x00000304 961444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR1 0x00000305 962444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR2 0x00000306 963444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_PERFCTR3 0x00000307 964444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR0 0x00000308 965444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR1 0x00000309 966444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR2 0x0000030a 967444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_PERFCTR3 0x0000030b 968444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR0 0x0000030c 969444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR1 0x0000030d 970444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR2 0x0000030e 971444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR3 0x0000030f 972444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR4 0x00000310 973444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_PERFCTR5 0x00000311 974444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR0 0x00000360 975444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR1 0x00000361 976444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR2 0x00000362 977444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_CCCR3 0x00000363 978444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR0 0x00000364 979444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR1 0x00000365 980444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR2 0x00000366 981444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_CCCR3 0x00000367 982444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR0 0x00000368 983444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR1 0x00000369 984444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR2 0x0000036a 985444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_CCCR3 0x0000036b 986444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR0 0x0000036c 987444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR1 0x0000036d 988444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR2 0x0000036e 989444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR3 0x0000036f 990444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR4 0x00000370 991444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_CCCR5 0x00000371 992444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ALF_ESCR0 0x000003ca 993444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ALF_ESCR1 0x000003cb 994444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_ESCR0 0x000003b2 995444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BPU_ESCR1 0x000003b3 996444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BSU_ESCR0 0x000003a0 997444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_BSU_ESCR1 0x000003a1 998444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR0 0x000003b8 999444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR1 0x000003b9 1000444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR2 0x000003cc 1001444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR3 0x000003cd 1002444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR4 0x000003e0 1003444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_CRU_ESCR5 0x000003e1 1004444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_DAC_ESCR0 0x000003a8 1005444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_DAC_ESCR1 0x000003a9 1006444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FIRM_ESCR0 0x000003a4 1007444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FIRM_ESCR1 0x000003a5 1008444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_ESCR0 0x000003a6 1009444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FLAME_ESCR1 0x000003a7 1010444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FSB_ESCR0 0x000003a2 1011444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_FSB_ESCR1 0x000003a3 1012444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_ESCR0 0x000003ba 1013444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IQ_ESCR1 0x000003bb 1014444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IS_ESCR0 0x000003b4 1015444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IS_ESCR1 0x000003b5 1016444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ITLB_ESCR0 0x000003b6 1017444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_ITLB_ESCR1 0x000003b7 1018444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IX_ESCR0 0x000003c8 1019444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_IX_ESCR1 0x000003c9 1020444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MOB_ESCR0 0x000003aa 1021444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MOB_ESCR1 0x000003ab 1022444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_ESCR0 0x000003c0 1023444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_MS_ESCR1 0x000003c1 1024444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PMH_ESCR0 0x000003ac 1025444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PMH_ESCR1 0x000003ad 1026444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_RAT_ESCR0 0x000003bc 1027444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_RAT_ESCR1 0x000003bd 1028444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SAAT_ESCR0 0x000003ae 1029444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SAAT_ESCR1 0x000003af 1030444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SSU_ESCR0 0x000003be 1031444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 1032444e2ff3SArnaldo Carvalho de Melo 1033444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TBPU_ESCR0 0x000003c2 1034444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TBPU_ESCR1 0x000003c3 1035444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TC_ESCR0 0x000003c4 1036444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_TC_ESCR1 0x000003c5 1037444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_U2L_ESCR0 0x000003b0 1038444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_U2L_ESCR1 0x000003b1 1039444e2ff3SArnaldo Carvalho de Melo 1040444e2ff3SArnaldo Carvalho de Melo #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 1041444e2ff3SArnaldo Carvalho de Melo 1042444e2ff3SArnaldo Carvalho de Melo /* Intel Core-based CPU performance counters */ 1043444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 1044444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 1045444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 104632b734e0SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 1047444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 1048444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 1049444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 1050444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 1051444e2ff3SArnaldo Carvalho de Melo 105232b734e0SArnaldo Carvalho de Melo #define MSR_PERF_METRICS 0x00000329 105332b734e0SArnaldo Carvalho de Melo 1054444e2ff3SArnaldo Carvalho de Melo /* PERF_GLOBAL_OVF_CTL bits */ 1055444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 1056444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 1057444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 1058444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 1059444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 1060444e2ff3SArnaldo Carvalho de Melo #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 1061444e2ff3SArnaldo Carvalho de Melo 1062444e2ff3SArnaldo Carvalho de Melo /* Geode defined MSRs */ 1063444e2ff3SArnaldo Carvalho de Melo #define MSR_GEODE_BUSCONT_CONF0 0x00001900 1064444e2ff3SArnaldo Carvalho de Melo 1065444e2ff3SArnaldo Carvalho de Melo /* Intel VT MSRs */ 1066444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_BASIC 0x00000480 1067444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 1068444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 1069444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 1070444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 1071444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC 0x00000485 1072444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 1073444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 1074444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 1075444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 1076444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 1077444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 1078444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 1079444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 1080444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 1081444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 1082444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 1083444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_VMFUNC 0x00000491 10847f7f86a7SArnaldo Carvalho de Melo #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 1085444e2ff3SArnaldo Carvalho de Melo 1086444e2ff3SArnaldo Carvalho de Melo /* VMX_BASIC bits and bitmasks */ 1087444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_VMCS_SIZE_SHIFT 32 1088444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_TRUE_CTLS (1ULL << 55) 1089444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_64 0x0001000000000000LLU 1090444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_SHIFT 50 1091444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 1092444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_MEM_TYPE_WB 6LLU 1093444e2ff3SArnaldo Carvalho de Melo #define VMX_BASIC_INOUT 0x0040000000000000LLU 1094444e2ff3SArnaldo Carvalho de Melo 1095a66558dcSArnaldo Carvalho de Melo /* Resctrl MSRs: */ 1096a66558dcSArnaldo Carvalho de Melo /* - Intel: */ 1097a66558dcSArnaldo Carvalho de Melo #define MSR_IA32_L3_QOS_CFG 0xc81 1098a66558dcSArnaldo Carvalho de Melo #define MSR_IA32_L2_QOS_CFG 0xc82 1099a66558dcSArnaldo Carvalho de Melo #define MSR_IA32_QM_EVTSEL 0xc8d 1100a66558dcSArnaldo Carvalho de Melo #define MSR_IA32_QM_CTR 0xc8e 1101a66558dcSArnaldo Carvalho de Melo #define MSR_IA32_PQR_ASSOC 0xc8f 1102a66558dcSArnaldo Carvalho de Melo #define MSR_IA32_L3_CBM_BASE 0xc90 1103a66558dcSArnaldo Carvalho de Melo #define MSR_IA32_L2_CBM_BASE 0xd10 1104a66558dcSArnaldo Carvalho de Melo #define MSR_IA32_MBA_THRTL_BASE 0xd50 1105a66558dcSArnaldo Carvalho de Melo 1106a66558dcSArnaldo Carvalho de Melo /* - AMD: */ 1107a66558dcSArnaldo Carvalho de Melo #define MSR_IA32_MBA_BW_BASE 0xc0000200 11083ee7cb4fSArnaldo Carvalho de Melo #define MSR_IA32_SMBA_BW_BASE 0xc0000280 11093ee7cb4fSArnaldo Carvalho de Melo #define MSR_IA32_EVT_CFG_BASE 0xc0000400 1110a66558dcSArnaldo Carvalho de Melo 1111444e2ff3SArnaldo Carvalho de Melo /* MSR_IA32_VMX_MISC bits */ 1112444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 1113444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 1114444e2ff3SArnaldo Carvalho de Melo #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 1115444e2ff3SArnaldo Carvalho de Melo /* AMD-V MSRs */ 1116444e2ff3SArnaldo Carvalho de Melo 1117444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_CR 0xc0010114 1118444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_IGNNE 0xc0010115 1119444e2ff3SArnaldo Carvalho de Melo #define MSR_VM_HSAVE_PA 0xc0010117 1120444e2ff3SArnaldo Carvalho de Melo 112161726144SArnaldo Carvalho de Melo /* Hardware Feedback Interface */ 112261726144SArnaldo Carvalho de Melo #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 112361726144SArnaldo Carvalho de Melo #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 112461726144SArnaldo Carvalho de Melo 1125a3a36565SArnaldo Carvalho de Melo /* x2APIC locked status */ 1126a3a36565SArnaldo Carvalho de Melo #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD 1127a3a36565SArnaldo Carvalho de Melo #define LEGACY_XAPIC_DISABLED BIT(0) /* 1128a3a36565SArnaldo Carvalho de Melo * x2APIC mode is locked and 1129a3a36565SArnaldo Carvalho de Melo * disabling x2APIC will cause 1130a3a36565SArnaldo Carvalho de Melo * a #GP 1131a3a36565SArnaldo Carvalho de Melo */ 1132a3a36565SArnaldo Carvalho de Melo 1133444e2ff3SArnaldo Carvalho de Melo #endif /* _ASM_X86_MSR_INDEX_H */ 1134