1f03e97dbSBorislav Petkov /*
2f03e97dbSBorislav Petkov * Netburst Performance Events (P4, old Xeon)
3f03e97dbSBorislav Petkov *
4f03e97dbSBorislav Petkov * Copyright (C) 2010 Parallels, Inc., Cyrill Gorcunov <gorcunov@openvz.org>
5f03e97dbSBorislav Petkov * Copyright (C) 2010 Intel Corporation, Lin Ming <ming.m.lin@intel.com>
6f03e97dbSBorislav Petkov *
7f03e97dbSBorislav Petkov * For licencing details see kernel-base/COPYING
8f03e97dbSBorislav Petkov */
9f03e97dbSBorislav Petkov
10f03e97dbSBorislav Petkov #include <linux/perf_event.h>
11f03e97dbSBorislav Petkov
12f03e97dbSBorislav Petkov #include <asm/perf_event_p4.h>
13f03e97dbSBorislav Petkov #include <asm/hardirq.h>
14f03e97dbSBorislav Petkov #include <asm/apic.h>
15f03e97dbSBorislav Petkov
1627f6d22bSBorislav Petkov #include "../perf_event.h"
17f03e97dbSBorislav Petkov
18f03e97dbSBorislav Petkov #define P4_CNTR_LIMIT 3
19f03e97dbSBorislav Petkov /*
20f03e97dbSBorislav Petkov * array indices: 0,1 - HT threads, used with HT enabled cpu
21f03e97dbSBorislav Petkov */
22f03e97dbSBorislav Petkov struct p4_event_bind {
23f03e97dbSBorislav Petkov unsigned int opcode; /* Event code and ESCR selector */
24f03e97dbSBorislav Petkov unsigned int escr_msr[2]; /* ESCR MSR for this event */
25f03e97dbSBorislav Petkov unsigned int escr_emask; /* valid ESCR EventMask bits */
26f03e97dbSBorislav Petkov unsigned int shared; /* event is shared across threads */
27*adcd7118SAlexey Dobriyan signed char cntr[2][P4_CNTR_LIMIT]; /* counter index (offset), -1 on absence */
28f03e97dbSBorislav Petkov };
29f03e97dbSBorislav Petkov
30f03e97dbSBorislav Petkov struct p4_pebs_bind {
31f03e97dbSBorislav Petkov unsigned int metric_pebs;
32f03e97dbSBorislav Petkov unsigned int metric_vert;
33f03e97dbSBorislav Petkov };
34f03e97dbSBorislav Petkov
35f03e97dbSBorislav Petkov /* it sets P4_PEBS_ENABLE_UOP_TAG as well */
36f03e97dbSBorislav Petkov #define P4_GEN_PEBS_BIND(name, pebs, vert) \
37f03e97dbSBorislav Petkov [P4_PEBS_METRIC__##name] = { \
38f03e97dbSBorislav Petkov .metric_pebs = pebs | P4_PEBS_ENABLE_UOP_TAG, \
39f03e97dbSBorislav Petkov .metric_vert = vert, \
40f03e97dbSBorislav Petkov }
41f03e97dbSBorislav Petkov
42f03e97dbSBorislav Petkov /*
43f03e97dbSBorislav Petkov * note we have P4_PEBS_ENABLE_UOP_TAG always set here
44f03e97dbSBorislav Petkov *
45f03e97dbSBorislav Petkov * it's needed for mapping P4_PEBS_CONFIG_METRIC_MASK bits of
46f03e97dbSBorislav Petkov * event configuration to find out which values are to be
47f03e97dbSBorislav Petkov * written into MSR_IA32_PEBS_ENABLE and MSR_P4_PEBS_MATRIX_VERT
48d9f6e12fSIngo Molnar * registers
49f03e97dbSBorislav Petkov */
50f03e97dbSBorislav Petkov static struct p4_pebs_bind p4_pebs_bind_map[] = {
51f03e97dbSBorislav Petkov P4_GEN_PEBS_BIND(1stl_cache_load_miss_retired, 0x0000001, 0x0000001),
52f03e97dbSBorislav Petkov P4_GEN_PEBS_BIND(2ndl_cache_load_miss_retired, 0x0000002, 0x0000001),
53f03e97dbSBorislav Petkov P4_GEN_PEBS_BIND(dtlb_load_miss_retired, 0x0000004, 0x0000001),
54f03e97dbSBorislav Petkov P4_GEN_PEBS_BIND(dtlb_store_miss_retired, 0x0000004, 0x0000002),
55f03e97dbSBorislav Petkov P4_GEN_PEBS_BIND(dtlb_all_miss_retired, 0x0000004, 0x0000003),
56f03e97dbSBorislav Petkov P4_GEN_PEBS_BIND(tagged_mispred_branch, 0x0018000, 0x0000010),
57f03e97dbSBorislav Petkov P4_GEN_PEBS_BIND(mob_load_replay_retired, 0x0000200, 0x0000001),
58f03e97dbSBorislav Petkov P4_GEN_PEBS_BIND(split_load_retired, 0x0000400, 0x0000001),
59f03e97dbSBorislav Petkov P4_GEN_PEBS_BIND(split_store_retired, 0x0000400, 0x0000002),
60f03e97dbSBorislav Petkov };
61f03e97dbSBorislav Petkov
62f03e97dbSBorislav Petkov /*
63f03e97dbSBorislav Petkov * Note that we don't use CCCR1 here, there is an
64f03e97dbSBorislav Petkov * exception for P4_BSQ_ALLOCATION but we just have
65f03e97dbSBorislav Petkov * no workaround
66f03e97dbSBorislav Petkov *
67f03e97dbSBorislav Petkov * consider this binding as resources which particular
68f03e97dbSBorislav Petkov * event may borrow, it doesn't contain EventMask,
69f03e97dbSBorislav Petkov * Tags and friends -- they are left to a caller
70f03e97dbSBorislav Petkov */
71f03e97dbSBorislav Petkov static struct p4_event_bind p4_event_bind_map[] = {
72f03e97dbSBorislav Petkov [P4_EVENT_TC_DELIVER_MODE] = {
73f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_TC_DELIVER_MODE),
74f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
75f03e97dbSBorislav Petkov .escr_emask =
76f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) |
77f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DB) |
78f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DI) |
79f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BD) |
80f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BB) |
81f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, BI) |
82f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, ID),
83f03e97dbSBorislav Petkov .shared = 1,
84f03e97dbSBorislav Petkov .cntr = { {4, 5, -1}, {6, 7, -1} },
85f03e97dbSBorislav Petkov },
86f03e97dbSBorislav Petkov [P4_EVENT_BPU_FETCH_REQUEST] = {
87f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST),
88f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_BPU_ESCR0, MSR_P4_BPU_ESCR1 },
89f03e97dbSBorislav Petkov .escr_emask =
90f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BPU_FETCH_REQUEST, TCMISS),
91f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
92f03e97dbSBorislav Petkov },
93f03e97dbSBorislav Petkov [P4_EVENT_ITLB_REFERENCE] = {
94f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_ITLB_REFERENCE),
95f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_ITLB_ESCR0, MSR_P4_ITLB_ESCR1 },
96f03e97dbSBorislav Petkov .escr_emask =
97f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, HIT) |
98f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, MISS) |
99f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, HIT_UK),
100f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
101f03e97dbSBorislav Petkov },
102f03e97dbSBorislav Petkov [P4_EVENT_MEMORY_CANCEL] = {
103f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_MEMORY_CANCEL),
104f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
105f03e97dbSBorislav Petkov .escr_emask =
106f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL) |
107f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_CANCEL, 64K_CONF),
108f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
109f03e97dbSBorislav Petkov },
110f03e97dbSBorislav Petkov [P4_EVENT_MEMORY_COMPLETE] = {
111f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_MEMORY_COMPLETE),
112f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
113f03e97dbSBorislav Petkov .escr_emask =
114f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_COMPLETE, LSC) |
115f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MEMORY_COMPLETE, SSC),
116f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
117f03e97dbSBorislav Petkov },
118f03e97dbSBorislav Petkov [P4_EVENT_LOAD_PORT_REPLAY] = {
119f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY),
120f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_SAAT_ESCR0, MSR_P4_SAAT_ESCR1 },
121f03e97dbSBorislav Petkov .escr_emask =
122f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD),
123f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
124f03e97dbSBorislav Petkov },
125f03e97dbSBorislav Petkov [P4_EVENT_STORE_PORT_REPLAY] = {
126f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY),
127f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_SAAT_ESCR0 , MSR_P4_SAAT_ESCR1 },
128f03e97dbSBorislav Petkov .escr_emask =
129f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST),
130f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
131f03e97dbSBorislav Petkov },
132f03e97dbSBorislav Petkov [P4_EVENT_MOB_LOAD_REPLAY] = {
133f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY),
134f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_MOB_ESCR0, MSR_P4_MOB_ESCR1 },
135f03e97dbSBorislav Petkov .escr_emask =
136f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, NO_STA) |
137f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, NO_STD) |
138f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA) |
139f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR),
140f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
141f03e97dbSBorislav Petkov },
142f03e97dbSBorislav Petkov [P4_EVENT_PAGE_WALK_TYPE] = {
143f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE),
144f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_PMH_ESCR0, MSR_P4_PMH_ESCR1 },
145f03e97dbSBorislav Petkov .escr_emask =
146f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_PAGE_WALK_TYPE, DTMISS) |
147f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_PAGE_WALK_TYPE, ITMISS),
148f03e97dbSBorislav Petkov .shared = 1,
149f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
150f03e97dbSBorislav Petkov },
151f03e97dbSBorislav Petkov [P4_EVENT_BSQ_CACHE_REFERENCE] = {
152f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE),
153f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR1 },
154f03e97dbSBorislav Petkov .escr_emask =
155f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |
156f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |
157f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |
158f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |
159f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |
160f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM) |
161f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |
162f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
163f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS),
164f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
165f03e97dbSBorislav Petkov },
166f03e97dbSBorislav Petkov [P4_EVENT_IOQ_ALLOCATION] = {
167f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_IOQ_ALLOCATION),
168f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
169f03e97dbSBorislav Petkov .escr_emask =
170f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, DEFAULT) |
171f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, ALL_READ) |
172f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE) |
173f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_UC) |
174f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WC) |
175f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WT) |
176f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WP) |
177f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, MEM_WB) |
178f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, OWN) |
179f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, OTHER) |
180f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ALLOCATION, PREFETCH),
181f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
182f03e97dbSBorislav Petkov },
183f03e97dbSBorislav Petkov [P4_EVENT_IOQ_ACTIVE_ENTRIES] = { /* shared ESCR */
184f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES),
185f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FSB_ESCR1, MSR_P4_FSB_ESCR1 },
186f03e97dbSBorislav Petkov .escr_emask =
187f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT) |
188f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ) |
189f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE) |
190f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC) |
191f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC) |
192f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT) |
193f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP) |
194f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB) |
195f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN) |
196f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER) |
197f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH),
198f03e97dbSBorislav Petkov .cntr = { {2, -1, -1}, {3, -1, -1} },
199f03e97dbSBorislav Petkov },
200f03e97dbSBorislav Petkov [P4_EVENT_FSB_DATA_ACTIVITY] = {
201f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY),
202f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
203f03e97dbSBorislav Petkov .escr_emask =
204f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV) |
205f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN) |
206f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER) |
207f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV) |
208f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN) |
209f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER),
210f03e97dbSBorislav Petkov .shared = 1,
211f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
212f03e97dbSBorislav Petkov },
213f03e97dbSBorislav Petkov [P4_EVENT_BSQ_ALLOCATION] = { /* shared ESCR, broken CCCR1 */
214f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_BSQ_ALLOCATION),
215f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR0 },
216f03e97dbSBorislav Petkov .escr_emask =
217f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0) |
218f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1) |
219f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0) |
220f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1) |
221f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE) |
222f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE) |
223f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE) |
224f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE) |
225f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE) |
226f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE) |
227f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0) |
228f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1) |
229f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2),
230f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {1, -1, -1} },
231f03e97dbSBorislav Petkov },
232f03e97dbSBorislav Petkov [P4_EVENT_BSQ_ACTIVE_ENTRIES] = { /* shared ESCR */
233f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES),
234f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_BSU_ESCR1 , MSR_P4_BSU_ESCR1 },
235f03e97dbSBorislav Petkov .escr_emask =
236f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0) |
237f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1) |
238f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0) |
239f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1) |
240f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE) |
241f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE) |
242f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE) |
243f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE) |
244f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE) |
245f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE) |
246f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0) |
247f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1) |
248f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2),
249f03e97dbSBorislav Petkov .cntr = { {2, -1, -1}, {3, -1, -1} },
250f03e97dbSBorislav Petkov },
251f03e97dbSBorislav Petkov [P4_EVENT_SSE_INPUT_ASSIST] = {
252f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST),
253f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
254f03e97dbSBorislav Petkov .escr_emask =
255f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_SSE_INPUT_ASSIST, ALL),
256f03e97dbSBorislav Petkov .shared = 1,
257f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
258f03e97dbSBorislav Petkov },
259f03e97dbSBorislav Petkov [P4_EVENT_PACKED_SP_UOP] = {
260f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_PACKED_SP_UOP),
261f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
262f03e97dbSBorislav Petkov .escr_emask =
263f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_PACKED_SP_UOP, ALL),
264f03e97dbSBorislav Petkov .shared = 1,
265f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
266f03e97dbSBorislav Petkov },
267f03e97dbSBorislav Petkov [P4_EVENT_PACKED_DP_UOP] = {
268f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_PACKED_DP_UOP),
269f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
270f03e97dbSBorislav Petkov .escr_emask =
271f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_PACKED_DP_UOP, ALL),
272f03e97dbSBorislav Petkov .shared = 1,
273f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
274f03e97dbSBorislav Petkov },
275f03e97dbSBorislav Petkov [P4_EVENT_SCALAR_SP_UOP] = {
276f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_SCALAR_SP_UOP),
277f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
278f03e97dbSBorislav Petkov .escr_emask =
279f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_SCALAR_SP_UOP, ALL),
280f03e97dbSBorislav Petkov .shared = 1,
281f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
282f03e97dbSBorislav Petkov },
283f03e97dbSBorislav Petkov [P4_EVENT_SCALAR_DP_UOP] = {
284f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_SCALAR_DP_UOP),
285f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
286f03e97dbSBorislav Petkov .escr_emask =
287f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_SCALAR_DP_UOP, ALL),
288f03e97dbSBorislav Petkov .shared = 1,
289f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
290f03e97dbSBorislav Petkov },
291f03e97dbSBorislav Petkov [P4_EVENT_64BIT_MMX_UOP] = {
292f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_64BIT_MMX_UOP),
293f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
294f03e97dbSBorislav Petkov .escr_emask =
295f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_64BIT_MMX_UOP, ALL),
296f03e97dbSBorislav Petkov .shared = 1,
297f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
298f03e97dbSBorislav Petkov },
299f03e97dbSBorislav Petkov [P4_EVENT_128BIT_MMX_UOP] = {
300f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_128BIT_MMX_UOP),
301f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
302f03e97dbSBorislav Petkov .escr_emask =
303f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_128BIT_MMX_UOP, ALL),
304f03e97dbSBorislav Petkov .shared = 1,
305f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
306f03e97dbSBorislav Petkov },
307f03e97dbSBorislav Petkov [P4_EVENT_X87_FP_UOP] = {
308f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_X87_FP_UOP),
309f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FIRM_ESCR0, MSR_P4_FIRM_ESCR1 },
310f03e97dbSBorislav Petkov .escr_emask =
311f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_X87_FP_UOP, ALL),
312f03e97dbSBorislav Petkov .shared = 1,
313f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
314f03e97dbSBorislav Petkov },
315f03e97dbSBorislav Petkov [P4_EVENT_TC_MISC] = {
316f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_TC_MISC),
317f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_TC_ESCR0, MSR_P4_TC_ESCR1 },
318f03e97dbSBorislav Petkov .escr_emask =
319f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_TC_MISC, FLUSH),
320f03e97dbSBorislav Petkov .cntr = { {4, 5, -1}, {6, 7, -1} },
321f03e97dbSBorislav Petkov },
322f03e97dbSBorislav Petkov [P4_EVENT_GLOBAL_POWER_EVENTS] = {
323f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS),
324f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
325f03e97dbSBorislav Petkov .escr_emask =
326f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING),
327f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
328f03e97dbSBorislav Petkov },
329f03e97dbSBorislav Petkov [P4_EVENT_TC_MS_XFER] = {
330f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_TC_MS_XFER),
331f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
332f03e97dbSBorislav Petkov .escr_emask =
333f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_TC_MS_XFER, CISC),
334f03e97dbSBorislav Petkov .cntr = { {4, 5, -1}, {6, 7, -1} },
335f03e97dbSBorislav Petkov },
336f03e97dbSBorislav Petkov [P4_EVENT_UOP_QUEUE_WRITES] = {
337f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES),
338f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_MS_ESCR0, MSR_P4_MS_ESCR1 },
339f03e97dbSBorislav Petkov .escr_emask =
340f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD) |
341f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER) |
342f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM),
343f03e97dbSBorislav Petkov .cntr = { {4, 5, -1}, {6, 7, -1} },
344f03e97dbSBorislav Petkov },
345f03e97dbSBorislav Petkov [P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE] = {
346f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE),
347f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR0 },
348f03e97dbSBorislav Petkov .escr_emask =
349f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL) |
350f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL) |
351f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN) |
352f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT),
353f03e97dbSBorislav Petkov .cntr = { {4, 5, -1}, {6, 7, -1} },
354f03e97dbSBorislav Petkov },
355f03e97dbSBorislav Petkov [P4_EVENT_RETIRED_BRANCH_TYPE] = {
356f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE),
357f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_TBPU_ESCR0 , MSR_P4_TBPU_ESCR1 },
358f03e97dbSBorislav Petkov .escr_emask =
359f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL) |
360f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CALL) |
361f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN) |
362f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT),
363f03e97dbSBorislav Petkov .cntr = { {4, 5, -1}, {6, 7, -1} },
364f03e97dbSBorislav Petkov },
365f03e97dbSBorislav Petkov [P4_EVENT_RESOURCE_STALL] = {
366f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_RESOURCE_STALL),
367f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_ALF_ESCR0, MSR_P4_ALF_ESCR1 },
368f03e97dbSBorislav Petkov .escr_emask =
369f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RESOURCE_STALL, SBFULL),
370f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
371f03e97dbSBorislav Petkov },
372f03e97dbSBorislav Petkov [P4_EVENT_WC_BUFFER] = {
373f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_WC_BUFFER),
374f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_DAC_ESCR0, MSR_P4_DAC_ESCR1 },
375f03e97dbSBorislav Petkov .escr_emask =
376f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_WC_BUFFER, WCB_EVICTS) |
377f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS),
378f03e97dbSBorislav Petkov .shared = 1,
379f03e97dbSBorislav Petkov .cntr = { {8, 9, -1}, {10, 11, -1} },
380f03e97dbSBorislav Petkov },
381f03e97dbSBorislav Petkov [P4_EVENT_B2B_CYCLES] = {
382f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_B2B_CYCLES),
383f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
384f03e97dbSBorislav Petkov .escr_emask = 0,
385f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
386f03e97dbSBorislav Petkov },
387f03e97dbSBorislav Petkov [P4_EVENT_BNR] = {
388f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_BNR),
389f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
390f03e97dbSBorislav Petkov .escr_emask = 0,
391f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
392f03e97dbSBorislav Petkov },
393f03e97dbSBorislav Petkov [P4_EVENT_SNOOP] = {
394f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_SNOOP),
395f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
396f03e97dbSBorislav Petkov .escr_emask = 0,
397f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
398f03e97dbSBorislav Petkov },
399f03e97dbSBorislav Petkov [P4_EVENT_RESPONSE] = {
400f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_RESPONSE),
401f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
402f03e97dbSBorislav Petkov .escr_emask = 0,
403f03e97dbSBorislav Petkov .cntr = { {0, -1, -1}, {2, -1, -1} },
404f03e97dbSBorislav Petkov },
405f03e97dbSBorislav Petkov [P4_EVENT_FRONT_END_EVENT] = {
406f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_FRONT_END_EVENT),
407f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
408f03e97dbSBorislav Petkov .escr_emask =
409f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FRONT_END_EVENT, NBOGUS) |
410f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FRONT_END_EVENT, BOGUS),
411f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
412f03e97dbSBorislav Petkov },
413f03e97dbSBorislav Petkov [P4_EVENT_EXECUTION_EVENT] = {
414f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_EXECUTION_EVENT),
415f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
416f03e97dbSBorislav Petkov .escr_emask =
417f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS0) |
418f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS1) |
419f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS2) |
420f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS3) |
421f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS0) |
422f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS1) |
423f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS2) |
424f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS3),
425f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
426f03e97dbSBorislav Petkov },
427f03e97dbSBorislav Petkov [P4_EVENT_REPLAY_EVENT] = {
428f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_REPLAY_EVENT),
429f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
430f03e97dbSBorislav Petkov .escr_emask =
431f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_REPLAY_EVENT, NBOGUS) |
432f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_REPLAY_EVENT, BOGUS),
433f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
434f03e97dbSBorislav Petkov },
435f03e97dbSBorislav Petkov [P4_EVENT_INSTR_RETIRED] = {
436f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_INSTR_RETIRED),
437f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
438f03e97dbSBorislav Petkov .escr_emask =
439f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG) |
440f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSTAG) |
441f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSNTAG) |
442f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSTAG),
443f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
444f03e97dbSBorislav Petkov },
445f03e97dbSBorislav Petkov [P4_EVENT_UOPS_RETIRED] = {
446f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_UOPS_RETIRED),
447f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
448f03e97dbSBorislav Petkov .escr_emask =
449f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_UOPS_RETIRED, NBOGUS) |
450f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_UOPS_RETIRED, BOGUS),
451f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
452f03e97dbSBorislav Petkov },
453f03e97dbSBorislav Petkov [P4_EVENT_UOP_TYPE] = {
454f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_UOP_TYPE),
455f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_RAT_ESCR0, MSR_P4_RAT_ESCR1 },
456f03e97dbSBorislav Petkov .escr_emask =
457f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_UOP_TYPE, TAGLOADS) |
458f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_UOP_TYPE, TAGSTORES),
459f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
460f03e97dbSBorislav Petkov },
461f03e97dbSBorislav Petkov [P4_EVENT_BRANCH_RETIRED] = {
462f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_BRANCH_RETIRED),
463f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
464f03e97dbSBorislav Petkov .escr_emask =
465f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMNP) |
466f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMNM) |
467f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMTP) |
468f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BRANCH_RETIRED, MMTM),
469f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
470f03e97dbSBorislav Petkov },
471f03e97dbSBorislav Petkov [P4_EVENT_MISPRED_BRANCH_RETIRED] = {
472f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED),
473f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
474f03e97dbSBorislav Petkov .escr_emask =
475f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS),
476f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
477f03e97dbSBorislav Petkov },
478f03e97dbSBorislav Petkov [P4_EVENT_X87_ASSIST] = {
479f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_X87_ASSIST),
480f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
481f03e97dbSBorislav Petkov .escr_emask =
482f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, FPSU) |
483f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, FPSO) |
484f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, POAO) |
485f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, POAU) |
486f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_X87_ASSIST, PREA),
487f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
488f03e97dbSBorislav Petkov },
489f03e97dbSBorislav Petkov [P4_EVENT_MACHINE_CLEAR] = {
490f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_MACHINE_CLEAR),
491f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR2, MSR_P4_CRU_ESCR3 },
492f03e97dbSBorislav Petkov .escr_emask =
493f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, CLEAR) |
494f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, MOCLEAR) |
495f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MACHINE_CLEAR, SMCLEAR),
496f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
497f03e97dbSBorislav Petkov },
498f03e97dbSBorislav Petkov [P4_EVENT_INSTR_COMPLETED] = {
499f03e97dbSBorislav Petkov .opcode = P4_OPCODE(P4_EVENT_INSTR_COMPLETED),
500f03e97dbSBorislav Petkov .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
501f03e97dbSBorislav Petkov .escr_emask =
502f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_COMPLETED, NBOGUS) |
503f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_COMPLETED, BOGUS),
504f03e97dbSBorislav Petkov .cntr = { {12, 13, 16}, {14, 15, 17} },
505f03e97dbSBorislav Petkov },
506f03e97dbSBorislav Petkov };
507f03e97dbSBorislav Petkov
508f03e97dbSBorislav Petkov #define P4_GEN_CACHE_EVENT(event, bit, metric) \
509f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(event) | \
510f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(event, bit)) | \
511f03e97dbSBorislav Petkov p4_config_pack_cccr(metric | \
512f03e97dbSBorislav Petkov P4_CCCR_ESEL(P4_OPCODE_ESEL(P4_OPCODE(event))))
513f03e97dbSBorislav Petkov
514f03e97dbSBorislav Petkov static __initconst const u64 p4_hw_cache_event_ids
515f03e97dbSBorislav Petkov [PERF_COUNT_HW_CACHE_MAX]
516f03e97dbSBorislav Petkov [PERF_COUNT_HW_CACHE_OP_MAX]
517f03e97dbSBorislav Petkov [PERF_COUNT_HW_CACHE_RESULT_MAX] =
518f03e97dbSBorislav Petkov {
519f03e97dbSBorislav Petkov [ C(L1D ) ] = {
520f03e97dbSBorislav Petkov [ C(OP_READ) ] = {
521f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0,
522f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
523f03e97dbSBorislav Petkov P4_PEBS_METRIC__1stl_cache_load_miss_retired),
524f03e97dbSBorislav Petkov },
525f03e97dbSBorislav Petkov },
526f03e97dbSBorislav Petkov [ C(LL ) ] = {
527f03e97dbSBorislav Petkov [ C(OP_READ) ] = {
528f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0,
529f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
530f03e97dbSBorislav Petkov P4_PEBS_METRIC__2ndl_cache_load_miss_retired),
531f03e97dbSBorislav Petkov },
532f03e97dbSBorislav Petkov },
533f03e97dbSBorislav Petkov [ C(DTLB) ] = {
534f03e97dbSBorislav Petkov [ C(OP_READ) ] = {
535f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0,
536f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
537f03e97dbSBorislav Petkov P4_PEBS_METRIC__dtlb_load_miss_retired),
538f03e97dbSBorislav Petkov },
539f03e97dbSBorislav Petkov [ C(OP_WRITE) ] = {
540f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = 0x0,
541f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_REPLAY_EVENT, NBOGUS,
542f03e97dbSBorislav Petkov P4_PEBS_METRIC__dtlb_store_miss_retired),
543f03e97dbSBorislav Petkov },
544f03e97dbSBorislav Petkov },
545f03e97dbSBorislav Petkov [ C(ITLB) ] = {
546f03e97dbSBorislav Petkov [ C(OP_READ) ] = {
547f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, HIT,
548f03e97dbSBorislav Petkov P4_PEBS_METRIC__none),
549f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, MISS,
550f03e97dbSBorislav Petkov P4_PEBS_METRIC__none),
551f03e97dbSBorislav Petkov },
552f03e97dbSBorislav Petkov [ C(OP_WRITE) ] = {
553f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = -1,
554f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = -1,
555f03e97dbSBorislav Petkov },
556f03e97dbSBorislav Petkov [ C(OP_PREFETCH) ] = {
557f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = -1,
558f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = -1,
559f03e97dbSBorislav Petkov },
560f03e97dbSBorislav Petkov },
561f03e97dbSBorislav Petkov [ C(NODE) ] = {
562f03e97dbSBorislav Petkov [ C(OP_READ) ] = {
563f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = -1,
564f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = -1,
565f03e97dbSBorislav Petkov },
566f03e97dbSBorislav Petkov [ C(OP_WRITE) ] = {
567f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = -1,
568f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = -1,
569f03e97dbSBorislav Petkov },
570f03e97dbSBorislav Petkov [ C(OP_PREFETCH) ] = {
571f03e97dbSBorislav Petkov [ C(RESULT_ACCESS) ] = -1,
572f03e97dbSBorislav Petkov [ C(RESULT_MISS) ] = -1,
573f03e97dbSBorislav Petkov },
574f03e97dbSBorislav Petkov },
575f03e97dbSBorislav Petkov };
576f03e97dbSBorislav Petkov
577f03e97dbSBorislav Petkov /*
578f03e97dbSBorislav Petkov * Because of Netburst being quite restricted in how many
579f03e97dbSBorislav Petkov * identical events may run simultaneously, we introduce event aliases,
580f03e97dbSBorislav Petkov * ie the different events which have the same functionality but
581f03e97dbSBorislav Petkov * utilize non-intersected resources (ESCR/CCCR/counter registers).
582f03e97dbSBorislav Petkov *
583f03e97dbSBorislav Petkov * This allow us to relax restrictions a bit and run two or more
584f03e97dbSBorislav Petkov * identical events together.
585f03e97dbSBorislav Petkov *
586f03e97dbSBorislav Petkov * Never set any custom internal bits such as P4_CONFIG_HT,
587f03e97dbSBorislav Petkov * P4_CONFIG_ALIASABLE or bits for P4_PEBS_METRIC, they are
588f03e97dbSBorislav Petkov * either up to date automatically or not applicable at all.
589f03e97dbSBorislav Petkov */
590b45e4c45SColin Ian King static struct p4_event_alias {
591f03e97dbSBorislav Petkov u64 original;
592f03e97dbSBorislav Petkov u64 alternative;
593f03e97dbSBorislav Petkov } p4_event_aliases[] = {
594f03e97dbSBorislav Petkov {
595f03e97dbSBorislav Petkov /*
596f03e97dbSBorislav Petkov * Non-halted cycles can be substituted with non-sleeping cycles (see
597f03e97dbSBorislav Petkov * Intel SDM Vol3b for details). We need this alias to be able
598f03e97dbSBorislav Petkov * to run nmi-watchdog and 'perf top' (or any other user space tool
599f03e97dbSBorislav Petkov * which is interested in running PERF_COUNT_HW_CPU_CYCLES)
600f03e97dbSBorislav Petkov * simultaneously.
601f03e97dbSBorislav Petkov */
602f03e97dbSBorislav Petkov .original =
603f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS) |
604f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)),
605f03e97dbSBorislav Petkov .alternative =
606f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_EXECUTION_EVENT) |
607f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS0)|
608f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS1)|
609f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS2)|
610f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS3)|
611f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS0) |
612f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS1) |
613f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS2) |
614f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS3))|
615f03e97dbSBorislav Petkov p4_config_pack_cccr(P4_CCCR_THRESHOLD(15) | P4_CCCR_COMPLEMENT |
616f03e97dbSBorislav Petkov P4_CCCR_COMPARE),
617f03e97dbSBorislav Petkov },
618f03e97dbSBorislav Petkov };
619f03e97dbSBorislav Petkov
p4_get_alias_event(u64 config)620f03e97dbSBorislav Petkov static u64 p4_get_alias_event(u64 config)
621f03e97dbSBorislav Petkov {
622f03e97dbSBorislav Petkov u64 config_match;
623f03e97dbSBorislav Petkov int i;
624f03e97dbSBorislav Petkov
625f03e97dbSBorislav Petkov /*
626f03e97dbSBorislav Petkov * Only event with special mark is allowed,
627f03e97dbSBorislav Petkov * we're to be sure it didn't come as malformed
628f03e97dbSBorislav Petkov * RAW event.
629f03e97dbSBorislav Petkov */
630f03e97dbSBorislav Petkov if (!(config & P4_CONFIG_ALIASABLE))
631f03e97dbSBorislav Petkov return 0;
632f03e97dbSBorislav Petkov
633f03e97dbSBorislav Petkov config_match = config & P4_CONFIG_EVENT_ALIAS_MASK;
634f03e97dbSBorislav Petkov
635f03e97dbSBorislav Petkov for (i = 0; i < ARRAY_SIZE(p4_event_aliases); i++) {
636f03e97dbSBorislav Petkov if (config_match == p4_event_aliases[i].original) {
637f03e97dbSBorislav Petkov config_match = p4_event_aliases[i].alternative;
638f03e97dbSBorislav Petkov break;
639f03e97dbSBorislav Petkov } else if (config_match == p4_event_aliases[i].alternative) {
640f03e97dbSBorislav Petkov config_match = p4_event_aliases[i].original;
641f03e97dbSBorislav Petkov break;
642f03e97dbSBorislav Petkov }
643f03e97dbSBorislav Petkov }
644f03e97dbSBorislav Petkov
645f03e97dbSBorislav Petkov if (i >= ARRAY_SIZE(p4_event_aliases))
646f03e97dbSBorislav Petkov return 0;
647f03e97dbSBorislav Petkov
648f03e97dbSBorislav Petkov return config_match | (config & P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS);
649f03e97dbSBorislav Petkov }
650f03e97dbSBorislav Petkov
651f03e97dbSBorislav Petkov static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
652f03e97dbSBorislav Petkov /* non-halted CPU clocks */
653f03e97dbSBorislav Petkov [PERF_COUNT_HW_CPU_CYCLES] =
654f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS) |
655f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING)) |
656f03e97dbSBorislav Petkov P4_CONFIG_ALIASABLE,
657f03e97dbSBorislav Petkov
658f03e97dbSBorislav Petkov /*
659f03e97dbSBorislav Petkov * retired instructions
660f03e97dbSBorislav Petkov * in a sake of simplicity we don't use the FSB tagging
661f03e97dbSBorislav Petkov */
662f03e97dbSBorislav Petkov [PERF_COUNT_HW_INSTRUCTIONS] =
663f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_INSTR_RETIRED) |
664f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG) |
665f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_INSTR_RETIRED, BOGUSNTAG)),
666f03e97dbSBorislav Petkov
667f03e97dbSBorislav Petkov /* cache hits */
668f03e97dbSBorislav Petkov [PERF_COUNT_HW_CACHE_REFERENCES] =
669f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
670f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |
671f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |
672f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |
673f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |
674f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |
675f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM)),
676f03e97dbSBorislav Petkov
677f03e97dbSBorislav Petkov /* cache misses */
678f03e97dbSBorislav Petkov [PERF_COUNT_HW_CACHE_MISSES] =
679f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_BSQ_CACHE_REFERENCE) |
680f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |
681f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
682f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS)),
683f03e97dbSBorislav Petkov
684f03e97dbSBorislav Petkov /* branch instructions retired */
685f03e97dbSBorislav Petkov [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =
686f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_RETIRED_BRANCH_TYPE) |
687f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL) |
688f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, CALL) |
689f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN) |
690f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT)),
691f03e97dbSBorislav Petkov
692f03e97dbSBorislav Petkov /* mispredicted branches retired */
693f03e97dbSBorislav Petkov [PERF_COUNT_HW_BRANCH_MISSES] =
694f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_MISPRED_BRANCH_RETIRED) |
695f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS)),
696f03e97dbSBorislav Petkov
697f03e97dbSBorislav Petkov /* bus ready clocks (cpu is driving #DRDY_DRV\#DRDY_OWN): */
698f03e97dbSBorislav Petkov [PERF_COUNT_HW_BUS_CYCLES] =
699f03e97dbSBorislav Petkov p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_FSB_DATA_ACTIVITY) |
700f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV) |
701f03e97dbSBorislav Petkov P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN)) |
702f03e97dbSBorislav Petkov p4_config_pack_cccr(P4_CCCR_EDGE | P4_CCCR_COMPARE),
703f03e97dbSBorislav Petkov };
704f03e97dbSBorislav Petkov
p4_config_get_bind(u64 config)705f03e97dbSBorislav Petkov static struct p4_event_bind *p4_config_get_bind(u64 config)
706f03e97dbSBorislav Petkov {
707f03e97dbSBorislav Petkov unsigned int evnt = p4_config_unpack_event(config);
708f03e97dbSBorislav Petkov struct p4_event_bind *bind = NULL;
709f03e97dbSBorislav Petkov
710f03e97dbSBorislav Petkov if (evnt < ARRAY_SIZE(p4_event_bind_map))
711f03e97dbSBorislav Petkov bind = &p4_event_bind_map[evnt];
712f03e97dbSBorislav Petkov
713f03e97dbSBorislav Petkov return bind;
714f03e97dbSBorislav Petkov }
715f03e97dbSBorislav Petkov
p4_pmu_event_map(int hw_event)716f03e97dbSBorislav Petkov static u64 p4_pmu_event_map(int hw_event)
717f03e97dbSBorislav Petkov {
718f03e97dbSBorislav Petkov struct p4_event_bind *bind;
719f03e97dbSBorislav Petkov unsigned int esel;
720f03e97dbSBorislav Petkov u64 config;
721f03e97dbSBorislav Petkov
722f03e97dbSBorislav Petkov config = p4_general_events[hw_event];
723f03e97dbSBorislav Petkov bind = p4_config_get_bind(config);
724f03e97dbSBorislav Petkov esel = P4_OPCODE_ESEL(bind->opcode);
725f03e97dbSBorislav Petkov config |= p4_config_pack_cccr(P4_CCCR_ESEL(esel));
726f03e97dbSBorislav Petkov
727f03e97dbSBorislav Petkov return config;
728f03e97dbSBorislav Petkov }
729f03e97dbSBorislav Petkov
730f03e97dbSBorislav Petkov /* check cpu model specifics */
p4_event_match_cpu_model(unsigned int event_idx)731f03e97dbSBorislav Petkov static bool p4_event_match_cpu_model(unsigned int event_idx)
732f03e97dbSBorislav Petkov {
733f03e97dbSBorislav Petkov /* INSTR_COMPLETED event only exist for model 3, 4, 6 (Prescott) */
734f03e97dbSBorislav Petkov if (event_idx == P4_EVENT_INSTR_COMPLETED) {
735f03e97dbSBorislav Petkov if (boot_cpu_data.x86_model != 3 &&
736f03e97dbSBorislav Petkov boot_cpu_data.x86_model != 4 &&
737f03e97dbSBorislav Petkov boot_cpu_data.x86_model != 6)
738f03e97dbSBorislav Petkov return false;
739f03e97dbSBorislav Petkov }
740f03e97dbSBorislav Petkov
741f03e97dbSBorislav Petkov /*
742f03e97dbSBorislav Petkov * For info
743f03e97dbSBorislav Petkov * - IQ_ESCR0, IQ_ESCR1 only for models 1 and 2
744f03e97dbSBorislav Petkov */
745f03e97dbSBorislav Petkov
746f03e97dbSBorislav Petkov return true;
747f03e97dbSBorislav Petkov }
748f03e97dbSBorislav Petkov
p4_validate_raw_event(struct perf_event * event)749f03e97dbSBorislav Petkov static int p4_validate_raw_event(struct perf_event *event)
750f03e97dbSBorislav Petkov {
751f03e97dbSBorislav Petkov unsigned int v, emask;
752f03e97dbSBorislav Petkov
753f03e97dbSBorislav Petkov /* User data may have out-of-bound event index */
754f03e97dbSBorislav Petkov v = p4_config_unpack_event(event->attr.config);
755f03e97dbSBorislav Petkov if (v >= ARRAY_SIZE(p4_event_bind_map))
756f03e97dbSBorislav Petkov return -EINVAL;
757f03e97dbSBorislav Petkov
758f03e97dbSBorislav Petkov /* It may be unsupported: */
759f03e97dbSBorislav Petkov if (!p4_event_match_cpu_model(v))
760f03e97dbSBorislav Petkov return -EINVAL;
761f03e97dbSBorislav Petkov
762f03e97dbSBorislav Petkov /*
763f03e97dbSBorislav Petkov * NOTE: P4_CCCR_THREAD_ANY has not the same meaning as
764f03e97dbSBorislav Petkov * in Architectural Performance Monitoring, it means not
765f03e97dbSBorislav Petkov * on _which_ logical cpu to count but rather _when_, ie it
766f03e97dbSBorislav Petkov * depends on logical cpu state -- count event if one cpu active,
767f03e97dbSBorislav Petkov * none, both or any, so we just allow user to pass any value
768f03e97dbSBorislav Petkov * desired.
769f03e97dbSBorislav Petkov *
770f03e97dbSBorislav Petkov * In turn we always set Tx_OS/Tx_USR bits bound to logical
771f03e97dbSBorislav Petkov * cpu without their propagation to another cpu
772f03e97dbSBorislav Petkov */
773f03e97dbSBorislav Petkov
774f03e97dbSBorislav Petkov /*
775f03e97dbSBorislav Petkov * if an event is shared across the logical threads
776f03e97dbSBorislav Petkov * the user needs special permissions to be able to use it
777f03e97dbSBorislav Petkov */
778f03e97dbSBorislav Petkov if (p4_ht_active() && p4_event_bind_map[v].shared) {
779da97e184SJoel Fernandes (Google) v = perf_allow_cpu(&event->attr);
780da97e184SJoel Fernandes (Google) if (v)
781da97e184SJoel Fernandes (Google) return v;
782f03e97dbSBorislav Petkov }
783f03e97dbSBorislav Petkov
784f03e97dbSBorislav Petkov /* ESCR EventMask bits may be invalid */
785f03e97dbSBorislav Petkov emask = p4_config_unpack_escr(event->attr.config) & P4_ESCR_EVENTMASK_MASK;
786f03e97dbSBorislav Petkov if (emask & ~p4_event_bind_map[v].escr_emask)
787f03e97dbSBorislav Petkov return -EINVAL;
788f03e97dbSBorislav Petkov
789f03e97dbSBorislav Petkov /*
790f03e97dbSBorislav Petkov * it may have some invalid PEBS bits
791f03e97dbSBorislav Petkov */
792f03e97dbSBorislav Petkov if (p4_config_pebs_has(event->attr.config, P4_PEBS_CONFIG_ENABLE))
793f03e97dbSBorislav Petkov return -EINVAL;
794f03e97dbSBorislav Petkov
795f03e97dbSBorislav Petkov v = p4_config_unpack_metric(event->attr.config);
796f03e97dbSBorislav Petkov if (v >= ARRAY_SIZE(p4_pebs_bind_map))
797f03e97dbSBorislav Petkov return -EINVAL;
798f03e97dbSBorislav Petkov
799f03e97dbSBorislav Petkov return 0;
800f03e97dbSBorislav Petkov }
801f03e97dbSBorislav Petkov
p4_hw_config(struct perf_event * event)802f03e97dbSBorislav Petkov static int p4_hw_config(struct perf_event *event)
803f03e97dbSBorislav Petkov {
804f03e97dbSBorislav Petkov int cpu = get_cpu();
805f03e97dbSBorislav Petkov int rc = 0;
806f03e97dbSBorislav Petkov u32 escr, cccr;
807f03e97dbSBorislav Petkov
808f03e97dbSBorislav Petkov /*
809f03e97dbSBorislav Petkov * the reason we use cpu that early is that: if we get scheduled
810f03e97dbSBorislav Petkov * first time on the same cpu -- we will not need swap thread
811f03e97dbSBorislav Petkov * specific flags in config (and will save some cpu cycles)
812f03e97dbSBorislav Petkov */
813f03e97dbSBorislav Petkov
814f03e97dbSBorislav Petkov cccr = p4_default_cccr_conf(cpu);
815f03e97dbSBorislav Petkov escr = p4_default_escr_conf(cpu, event->attr.exclude_kernel,
816f03e97dbSBorislav Petkov event->attr.exclude_user);
817f03e97dbSBorislav Petkov event->hw.config = p4_config_pack_escr(escr) |
818f03e97dbSBorislav Petkov p4_config_pack_cccr(cccr);
819f03e97dbSBorislav Petkov
820f03e97dbSBorislav Petkov if (p4_ht_active() && p4_ht_thread(cpu))
821f03e97dbSBorislav Petkov event->hw.config = p4_set_ht_bit(event->hw.config);
822f03e97dbSBorislav Petkov
823f03e97dbSBorislav Petkov if (event->attr.type == PERF_TYPE_RAW) {
824f03e97dbSBorislav Petkov struct p4_event_bind *bind;
825f03e97dbSBorislav Petkov unsigned int esel;
826f03e97dbSBorislav Petkov /*
827f03e97dbSBorislav Petkov * Clear bits we reserve to be managed by kernel itself
828f03e97dbSBorislav Petkov * and never allowed from a user space
829f03e97dbSBorislav Petkov */
830f03e97dbSBorislav Petkov event->attr.config &= P4_CONFIG_MASK;
831f03e97dbSBorislav Petkov
832f03e97dbSBorislav Petkov rc = p4_validate_raw_event(event);
833f03e97dbSBorislav Petkov if (rc)
834f03e97dbSBorislav Petkov goto out;
835f03e97dbSBorislav Petkov
836f03e97dbSBorislav Petkov /*
837f03e97dbSBorislav Petkov * Note that for RAW events we allow user to use P4_CCCR_RESERVED
838f03e97dbSBorislav Petkov * bits since we keep additional info here (for cache events and etc)
839f03e97dbSBorislav Petkov */
840f03e97dbSBorislav Petkov event->hw.config |= event->attr.config;
841f03e97dbSBorislav Petkov bind = p4_config_get_bind(event->attr.config);
842f03e97dbSBorislav Petkov if (!bind) {
843f03e97dbSBorislav Petkov rc = -EINVAL;
844f03e97dbSBorislav Petkov goto out;
845f03e97dbSBorislav Petkov }
846f03e97dbSBorislav Petkov esel = P4_OPCODE_ESEL(bind->opcode);
847f03e97dbSBorislav Petkov event->hw.config |= p4_config_pack_cccr(P4_CCCR_ESEL(esel));
848f03e97dbSBorislav Petkov }
849f03e97dbSBorislav Petkov
850f03e97dbSBorislav Petkov rc = x86_setup_perfctr(event);
851f03e97dbSBorislav Petkov out:
852f03e97dbSBorislav Petkov put_cpu();
853f03e97dbSBorislav Petkov return rc;
854f03e97dbSBorislav Petkov }
855f03e97dbSBorislav Petkov
p4_pmu_clear_cccr_ovf(struct hw_perf_event * hwc)856f03e97dbSBorislav Petkov static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
857f03e97dbSBorislav Petkov {
858f03e97dbSBorislav Petkov u64 v;
859f03e97dbSBorislav Petkov
860f03e97dbSBorislav Petkov /* an official way for overflow indication */
861f03e97dbSBorislav Petkov rdmsrl(hwc->config_base, v);
862f03e97dbSBorislav Petkov if (v & P4_CCCR_OVF) {
863f03e97dbSBorislav Petkov wrmsrl(hwc->config_base, v & ~P4_CCCR_OVF);
864f03e97dbSBorislav Petkov return 1;
865f03e97dbSBorislav Petkov }
866f03e97dbSBorislav Petkov
867f03e97dbSBorislav Petkov /*
868f03e97dbSBorislav Petkov * In some circumstances the overflow might issue an NMI but did
869f03e97dbSBorislav Petkov * not set P4_CCCR_OVF bit. Because a counter holds a negative value
870f03e97dbSBorislav Petkov * we simply check for high bit being set, if it's cleared it means
871f03e97dbSBorislav Petkov * the counter has reached zero value and continued counting before
872f03e97dbSBorislav Petkov * real NMI signal was received:
873f03e97dbSBorislav Petkov */
874f03e97dbSBorislav Petkov rdmsrl(hwc->event_base, v);
875f03e97dbSBorislav Petkov if (!(v & ARCH_P4_UNFLAGGED_BIT))
876f03e97dbSBorislav Petkov return 1;
877f03e97dbSBorislav Petkov
878f03e97dbSBorislav Petkov return 0;
879f03e97dbSBorislav Petkov }
880f03e97dbSBorislav Petkov
p4_pmu_disable_pebs(void)881f03e97dbSBorislav Petkov static void p4_pmu_disable_pebs(void)
882f03e97dbSBorislav Petkov {
883f03e97dbSBorislav Petkov /*
884f03e97dbSBorislav Petkov * FIXME
885f03e97dbSBorislav Petkov *
886f03e97dbSBorislav Petkov * It's still allowed that two threads setup same cache
887f03e97dbSBorislav Petkov * events so we can't simply clear metrics until we knew
888f03e97dbSBorislav Petkov * no one is depending on us, so we need kind of counter
889f03e97dbSBorislav Petkov * for "ReplayEvent" users.
890f03e97dbSBorislav Petkov *
891f03e97dbSBorislav Petkov * What is more complex -- RAW events, if user (for some
892f03e97dbSBorislav Petkov * reason) will pass some cache event metric with improper
893f03e97dbSBorislav Petkov * event opcode -- it's fine from hardware point of view
894f03e97dbSBorislav Petkov * but completely nonsense from "meaning" of such action.
895f03e97dbSBorislav Petkov *
896f03e97dbSBorislav Petkov * So at moment let leave metrics turned on forever -- it's
897f03e97dbSBorislav Petkov * ok for now but need to be revisited!
898f03e97dbSBorislav Petkov *
899f03e97dbSBorislav Petkov * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, 0);
900f03e97dbSBorislav Petkov * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, 0);
901f03e97dbSBorislav Petkov */
902f03e97dbSBorislav Petkov }
903f03e97dbSBorislav Petkov
p4_pmu_disable_event(struct perf_event * event)904f03e97dbSBorislav Petkov static inline void p4_pmu_disable_event(struct perf_event *event)
905f03e97dbSBorislav Petkov {
906f03e97dbSBorislav Petkov struct hw_perf_event *hwc = &event->hw;
907f03e97dbSBorislav Petkov
908f03e97dbSBorislav Petkov /*
909f03e97dbSBorislav Petkov * If event gets disabled while counter is in overflowed
910f03e97dbSBorislav Petkov * state we need to clear P4_CCCR_OVF, otherwise interrupt get
911f03e97dbSBorislav Petkov * asserted again and again
912f03e97dbSBorislav Petkov */
913f03e97dbSBorislav Petkov (void)wrmsrl_safe(hwc->config_base,
914f03e97dbSBorislav Petkov p4_config_unpack_cccr(hwc->config) & ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
915f03e97dbSBorislav Petkov }
916f03e97dbSBorislav Petkov
p4_pmu_disable_all(void)917f03e97dbSBorislav Petkov static void p4_pmu_disable_all(void)
918f03e97dbSBorislav Petkov {
919f03e97dbSBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
920f03e97dbSBorislav Petkov int idx;
921f03e97dbSBorislav Petkov
922f03e97dbSBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) {
923f03e97dbSBorislav Petkov struct perf_event *event = cpuc->events[idx];
924f03e97dbSBorislav Petkov if (!test_bit(idx, cpuc->active_mask))
925f03e97dbSBorislav Petkov continue;
926f03e97dbSBorislav Petkov p4_pmu_disable_event(event);
927f03e97dbSBorislav Petkov }
928f03e97dbSBorislav Petkov
929f03e97dbSBorislav Petkov p4_pmu_disable_pebs();
930f03e97dbSBorislav Petkov }
931f03e97dbSBorislav Petkov
932f03e97dbSBorislav Petkov /* configuration must be valid */
p4_pmu_enable_pebs(u64 config)933f03e97dbSBorislav Petkov static void p4_pmu_enable_pebs(u64 config)
934f03e97dbSBorislav Petkov {
935f03e97dbSBorislav Petkov struct p4_pebs_bind *bind;
936f03e97dbSBorislav Petkov unsigned int idx;
937f03e97dbSBorislav Petkov
938f03e97dbSBorislav Petkov BUILD_BUG_ON(P4_PEBS_METRIC__max > P4_PEBS_CONFIG_METRIC_MASK);
939f03e97dbSBorislav Petkov
940f03e97dbSBorislav Petkov idx = p4_config_unpack_metric(config);
941f03e97dbSBorislav Petkov if (idx == P4_PEBS_METRIC__none)
942f03e97dbSBorislav Petkov return;
943f03e97dbSBorislav Petkov
944f03e97dbSBorislav Petkov bind = &p4_pebs_bind_map[idx];
945f03e97dbSBorislav Petkov
946f03e97dbSBorislav Petkov (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs);
947f03e97dbSBorislav Petkov (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert);
948f03e97dbSBorislav Petkov }
949f03e97dbSBorislav Petkov
__p4_pmu_enable_event(struct perf_event * event)95046ade474SKan Liang static void __p4_pmu_enable_event(struct perf_event *event)
951f03e97dbSBorislav Petkov {
952f03e97dbSBorislav Petkov struct hw_perf_event *hwc = &event->hw;
953f03e97dbSBorislav Petkov int thread = p4_ht_config_thread(hwc->config);
954f03e97dbSBorislav Petkov u64 escr_conf = p4_config_unpack_escr(p4_clear_ht_bit(hwc->config));
955f03e97dbSBorislav Petkov unsigned int idx = p4_config_unpack_event(hwc->config);
956f03e97dbSBorislav Petkov struct p4_event_bind *bind;
957f03e97dbSBorislav Petkov u64 escr_addr, cccr;
958f03e97dbSBorislav Petkov
959f03e97dbSBorislav Petkov bind = &p4_event_bind_map[idx];
960f03e97dbSBorislav Petkov escr_addr = bind->escr_msr[thread];
961f03e97dbSBorislav Petkov
962f03e97dbSBorislav Petkov /*
963f03e97dbSBorislav Petkov * - we dont support cascaded counters yet
964f03e97dbSBorislav Petkov * - and counter 1 is broken (erratum)
965f03e97dbSBorislav Petkov */
966f03e97dbSBorislav Petkov WARN_ON_ONCE(p4_is_event_cascaded(hwc->config));
967f03e97dbSBorislav Petkov WARN_ON_ONCE(hwc->idx == 1);
968f03e97dbSBorislav Petkov
969f03e97dbSBorislav Petkov /* we need a real Event value */
970f03e97dbSBorislav Petkov escr_conf &= ~P4_ESCR_EVENT_MASK;
971f03e97dbSBorislav Petkov escr_conf |= P4_ESCR_EVENT(P4_OPCODE_EVNT(bind->opcode));
972f03e97dbSBorislav Petkov
973f03e97dbSBorislav Petkov cccr = p4_config_unpack_cccr(hwc->config);
974f03e97dbSBorislav Petkov
975f03e97dbSBorislav Petkov /*
976f03e97dbSBorislav Petkov * it could be Cache event so we need to write metrics
977f03e97dbSBorislav Petkov * into additional MSRs
978f03e97dbSBorislav Petkov */
979f03e97dbSBorislav Petkov p4_pmu_enable_pebs(hwc->config);
980f03e97dbSBorislav Petkov
981f03e97dbSBorislav Petkov (void)wrmsrl_safe(escr_addr, escr_conf);
982f03e97dbSBorislav Petkov (void)wrmsrl_safe(hwc->config_base,
983f03e97dbSBorislav Petkov (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE);
984f03e97dbSBorislav Petkov }
985f03e97dbSBorislav Petkov
98646ade474SKan Liang static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(X86_PMC_IDX_MAX)], p4_running);
98746ade474SKan Liang
p4_pmu_enable_event(struct perf_event * event)98846ade474SKan Liang static void p4_pmu_enable_event(struct perf_event *event)
98946ade474SKan Liang {
99046ade474SKan Liang int idx = event->hw.idx;
99146ade474SKan Liang
99246ade474SKan Liang __set_bit(idx, per_cpu(p4_running, smp_processor_id()));
99346ade474SKan Liang __p4_pmu_enable_event(event);
99446ade474SKan Liang }
99546ade474SKan Liang
p4_pmu_enable_all(int added)996f03e97dbSBorislav Petkov static void p4_pmu_enable_all(int added)
997f03e97dbSBorislav Petkov {
998f03e97dbSBorislav Petkov struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
999f03e97dbSBorislav Petkov int idx;
1000f03e97dbSBorislav Petkov
1001f03e97dbSBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1002f03e97dbSBorislav Petkov struct perf_event *event = cpuc->events[idx];
1003f03e97dbSBorislav Petkov if (!test_bit(idx, cpuc->active_mask))
1004f03e97dbSBorislav Petkov continue;
100546ade474SKan Liang __p4_pmu_enable_event(event);
1006f03e97dbSBorislav Petkov }
1007f03e97dbSBorislav Petkov }
1008f03e97dbSBorislav Petkov
p4_pmu_set_period(struct perf_event * event)1009dbf4e792SPeter Zijlstra static int p4_pmu_set_period(struct perf_event *event)
1010dbf4e792SPeter Zijlstra {
1011dbf4e792SPeter Zijlstra struct hw_perf_event *hwc = &event->hw;
1012dbf4e792SPeter Zijlstra s64 left = this_cpu_read(pmc_prev_left[hwc->idx]);
1013dbf4e792SPeter Zijlstra int ret;
1014dbf4e792SPeter Zijlstra
1015dbf4e792SPeter Zijlstra ret = x86_perf_event_set_period(event);
1016dbf4e792SPeter Zijlstra
1017dbf4e792SPeter Zijlstra if (hwc->event_base) {
1018dbf4e792SPeter Zijlstra /*
1019dbf4e792SPeter Zijlstra * This handles erratum N15 in intel doc 249199-029,
1020dbf4e792SPeter Zijlstra * the counter may not be updated correctly on write
1021dbf4e792SPeter Zijlstra * so we need a second write operation to do the trick
1022dbf4e792SPeter Zijlstra * (the official workaround didn't work)
1023dbf4e792SPeter Zijlstra *
1024dbf4e792SPeter Zijlstra * the former idea is taken from OProfile code
1025dbf4e792SPeter Zijlstra */
1026dbf4e792SPeter Zijlstra wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1027dbf4e792SPeter Zijlstra }
1028dbf4e792SPeter Zijlstra
1029dbf4e792SPeter Zijlstra return ret;
1030dbf4e792SPeter Zijlstra }
1031dbf4e792SPeter Zijlstra
p4_pmu_handle_irq(struct pt_regs * regs)1032f03e97dbSBorislav Petkov static int p4_pmu_handle_irq(struct pt_regs *regs)
1033f03e97dbSBorislav Petkov {
1034f03e97dbSBorislav Petkov struct perf_sample_data data;
1035f03e97dbSBorislav Petkov struct cpu_hw_events *cpuc;
1036f03e97dbSBorislav Petkov struct perf_event *event;
1037f03e97dbSBorislav Petkov struct hw_perf_event *hwc;
1038f03e97dbSBorislav Petkov int idx, handled = 0;
1039f03e97dbSBorislav Petkov u64 val;
1040f03e97dbSBorislav Petkov
1041f03e97dbSBorislav Petkov cpuc = this_cpu_ptr(&cpu_hw_events);
1042f03e97dbSBorislav Petkov
1043f03e97dbSBorislav Petkov for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1044f03e97dbSBorislav Petkov int overflow;
1045f03e97dbSBorislav Petkov
1046f03e97dbSBorislav Petkov if (!test_bit(idx, cpuc->active_mask)) {
1047f03e97dbSBorislav Petkov /* catch in-flight IRQs */
104846ade474SKan Liang if (__test_and_clear_bit(idx, per_cpu(p4_running, smp_processor_id())))
1049f03e97dbSBorislav Petkov handled++;
1050f03e97dbSBorislav Petkov continue;
1051f03e97dbSBorislav Petkov }
1052f03e97dbSBorislav Petkov
1053f03e97dbSBorislav Petkov event = cpuc->events[idx];
1054f03e97dbSBorislav Petkov hwc = &event->hw;
1055f03e97dbSBorislav Petkov
1056f03e97dbSBorislav Petkov WARN_ON_ONCE(hwc->idx != idx);
1057f03e97dbSBorislav Petkov
1058f03e97dbSBorislav Petkov /* it might be unflagged overflow */
1059f03e97dbSBorislav Petkov overflow = p4_pmu_clear_cccr_ovf(hwc);
1060f03e97dbSBorislav Petkov
1061f03e97dbSBorislav Petkov val = x86_perf_event_update(event);
1062f03e97dbSBorislav Petkov if (!overflow && (val & (1ULL << (x86_pmu.cntval_bits - 1))))
1063f03e97dbSBorislav Petkov continue;
1064f03e97dbSBorislav Petkov
1065f03e97dbSBorislav Petkov handled += overflow;
1066f03e97dbSBorislav Petkov
1067f03e97dbSBorislav Petkov /* event overflow for sure */
1068f03e97dbSBorislav Petkov perf_sample_data_init(&data, 0, hwc->last_period);
1069f03e97dbSBorislav Petkov
1070dbf4e792SPeter Zijlstra if (!static_call(x86_pmu_set_period)(event))
1071f03e97dbSBorislav Petkov continue;
1072f03e97dbSBorislav Petkov
1073f03e97dbSBorislav Petkov
1074f03e97dbSBorislav Petkov if (perf_event_overflow(event, &data, regs))
1075f03e97dbSBorislav Petkov x86_pmu_stop(event, 0);
1076f03e97dbSBorislav Petkov }
1077f03e97dbSBorislav Petkov
1078f03e97dbSBorislav Petkov if (handled)
1079f03e97dbSBorislav Petkov inc_irq_stat(apic_perf_irqs);
1080f03e97dbSBorislav Petkov
1081f03e97dbSBorislav Petkov /*
1082f03e97dbSBorislav Petkov * When dealing with the unmasking of the LVTPC on P4 perf hw, it has
1083f03e97dbSBorislav Petkov * been observed that the OVF bit flag has to be cleared first _before_
1084f03e97dbSBorislav Petkov * the LVTPC can be unmasked.
1085f03e97dbSBorislav Petkov *
1086f03e97dbSBorislav Petkov * The reason is the NMI line will continue to be asserted while the OVF
1087f03e97dbSBorislav Petkov * bit is set. This causes a second NMI to generate if the LVTPC is
1088f03e97dbSBorislav Petkov * unmasked before the OVF bit is cleared, leading to unknown NMI
1089f03e97dbSBorislav Petkov * messages.
1090f03e97dbSBorislav Petkov */
1091f03e97dbSBorislav Petkov apic_write(APIC_LVTPC, APIC_DM_NMI);
1092f03e97dbSBorislav Petkov
1093f03e97dbSBorislav Petkov return handled;
1094f03e97dbSBorislav Petkov }
1095f03e97dbSBorislav Petkov
1096f03e97dbSBorislav Petkov /*
1097f03e97dbSBorislav Petkov * swap thread specific fields according to a thread
1098f03e97dbSBorislav Petkov * we are going to run on
1099f03e97dbSBorislav Petkov */
p4_pmu_swap_config_ts(struct hw_perf_event * hwc,int cpu)1100f03e97dbSBorislav Petkov static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
1101f03e97dbSBorislav Petkov {
1102f03e97dbSBorislav Petkov u32 escr, cccr;
1103f03e97dbSBorislav Petkov
1104f03e97dbSBorislav Petkov /*
1105f03e97dbSBorislav Petkov * we either lucky and continue on same cpu or no HT support
1106f03e97dbSBorislav Petkov */
1107f03e97dbSBorislav Petkov if (!p4_should_swap_ts(hwc->config, cpu))
1108f03e97dbSBorislav Petkov return;
1109f03e97dbSBorislav Petkov
1110f03e97dbSBorislav Petkov /*
1111f03e97dbSBorislav Petkov * the event is migrated from an another logical
1112f03e97dbSBorislav Petkov * cpu, so we need to swap thread specific flags
1113f03e97dbSBorislav Petkov */
1114f03e97dbSBorislav Petkov
1115f03e97dbSBorislav Petkov escr = p4_config_unpack_escr(hwc->config);
1116f03e97dbSBorislav Petkov cccr = p4_config_unpack_cccr(hwc->config);
1117f03e97dbSBorislav Petkov
1118f03e97dbSBorislav Petkov if (p4_ht_thread(cpu)) {
1119f03e97dbSBorislav Petkov cccr &= ~P4_CCCR_OVF_PMI_T0;
1120f03e97dbSBorislav Petkov cccr |= P4_CCCR_OVF_PMI_T1;
1121f03e97dbSBorislav Petkov if (escr & P4_ESCR_T0_OS) {
1122f03e97dbSBorislav Petkov escr &= ~P4_ESCR_T0_OS;
1123f03e97dbSBorislav Petkov escr |= P4_ESCR_T1_OS;
1124f03e97dbSBorislav Petkov }
1125f03e97dbSBorislav Petkov if (escr & P4_ESCR_T0_USR) {
1126f03e97dbSBorislav Petkov escr &= ~P4_ESCR_T0_USR;
1127f03e97dbSBorislav Petkov escr |= P4_ESCR_T1_USR;
1128f03e97dbSBorislav Petkov }
1129f03e97dbSBorislav Petkov hwc->config = p4_config_pack_escr(escr);
1130f03e97dbSBorislav Petkov hwc->config |= p4_config_pack_cccr(cccr);
1131f03e97dbSBorislav Petkov hwc->config |= P4_CONFIG_HT;
1132f03e97dbSBorislav Petkov } else {
1133f03e97dbSBorislav Petkov cccr &= ~P4_CCCR_OVF_PMI_T1;
1134f03e97dbSBorislav Petkov cccr |= P4_CCCR_OVF_PMI_T0;
1135f03e97dbSBorislav Petkov if (escr & P4_ESCR_T1_OS) {
1136f03e97dbSBorislav Petkov escr &= ~P4_ESCR_T1_OS;
1137f03e97dbSBorislav Petkov escr |= P4_ESCR_T0_OS;
1138f03e97dbSBorislav Petkov }
1139f03e97dbSBorislav Petkov if (escr & P4_ESCR_T1_USR) {
1140f03e97dbSBorislav Petkov escr &= ~P4_ESCR_T1_USR;
1141f03e97dbSBorislav Petkov escr |= P4_ESCR_T0_USR;
1142f03e97dbSBorislav Petkov }
1143f03e97dbSBorislav Petkov hwc->config = p4_config_pack_escr(escr);
1144f03e97dbSBorislav Petkov hwc->config |= p4_config_pack_cccr(cccr);
1145f03e97dbSBorislav Petkov hwc->config &= ~P4_CONFIG_HT;
1146f03e97dbSBorislav Petkov }
1147f03e97dbSBorislav Petkov }
1148f03e97dbSBorislav Petkov
1149f03e97dbSBorislav Petkov /*
1150f03e97dbSBorislav Petkov * ESCR address hashing is tricky, ESCRs are not sequential
1151f03e97dbSBorislav Petkov * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03a0) and
1152f03e97dbSBorislav Petkov * the metric between any ESCRs is laid in range [0xa0,0xe1]
1153f03e97dbSBorislav Petkov *
1154f03e97dbSBorislav Petkov * so we make ~70% filled hashtable
1155f03e97dbSBorislav Petkov */
1156f03e97dbSBorislav Petkov
1157f03e97dbSBorislav Petkov #define P4_ESCR_MSR_BASE 0x000003a0
1158f03e97dbSBorislav Petkov #define P4_ESCR_MSR_MAX 0x000003e1
1159f03e97dbSBorislav Petkov #define P4_ESCR_MSR_TABLE_SIZE (P4_ESCR_MSR_MAX - P4_ESCR_MSR_BASE + 1)
1160f03e97dbSBorislav Petkov #define P4_ESCR_MSR_IDX(msr) (msr - P4_ESCR_MSR_BASE)
1161f03e97dbSBorislav Petkov #define P4_ESCR_MSR_TABLE_ENTRY(msr) [P4_ESCR_MSR_IDX(msr)] = msr
1162f03e97dbSBorislav Petkov
1163f03e97dbSBorislav Petkov static const unsigned int p4_escr_table[P4_ESCR_MSR_TABLE_SIZE] = {
1164f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ALF_ESCR0),
1165f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ALF_ESCR1),
1166f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BPU_ESCR0),
1167f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BPU_ESCR1),
1168f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BSU_ESCR0),
1169f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_BSU_ESCR1),
1170f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR0),
1171f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR1),
1172f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR2),
1173f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR3),
1174f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR4),
1175f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_CRU_ESCR5),
1176f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_DAC_ESCR0),
1177f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_DAC_ESCR1),
1178f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FIRM_ESCR0),
1179f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FIRM_ESCR1),
1180f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FLAME_ESCR0),
1181f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FLAME_ESCR1),
1182f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR0),
1183f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_FSB_ESCR1),
1184f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IQ_ESCR0),
1185f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IQ_ESCR1),
1186f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IS_ESCR0),
1187f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IS_ESCR1),
1188f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ITLB_ESCR0),
1189f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_ITLB_ESCR1),
1190f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IX_ESCR0),
1191f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_IX_ESCR1),
1192f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MOB_ESCR0),
1193f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MOB_ESCR1),
1194f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MS_ESCR0),
1195f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_MS_ESCR1),
1196f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_PMH_ESCR0),
1197f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_PMH_ESCR1),
1198f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_RAT_ESCR0),
1199f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_RAT_ESCR1),
1200f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SAAT_ESCR0),
1201f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SAAT_ESCR1),
1202f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SSU_ESCR0),
1203f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_SSU_ESCR1),
1204f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR0),
1205f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TBPU_ESCR1),
1206f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TC_ESCR0),
1207f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_TC_ESCR1),
1208f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_U2L_ESCR0),
1209f03e97dbSBorislav Petkov P4_ESCR_MSR_TABLE_ENTRY(MSR_P4_U2L_ESCR1),
1210f03e97dbSBorislav Petkov };
1211f03e97dbSBorislav Petkov
p4_get_escr_idx(unsigned int addr)1212f03e97dbSBorislav Petkov static int p4_get_escr_idx(unsigned int addr)
1213f03e97dbSBorislav Petkov {
1214f03e97dbSBorislav Petkov unsigned int idx = P4_ESCR_MSR_IDX(addr);
1215f03e97dbSBorislav Petkov
1216f03e97dbSBorislav Petkov if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE ||
1217f03e97dbSBorislav Petkov !p4_escr_table[idx] ||
1218f03e97dbSBorislav Petkov p4_escr_table[idx] != addr)) {
1219f03e97dbSBorislav Petkov WARN_ONCE(1, "P4 PMU: Wrong address passed: %x\n", addr);
1220f03e97dbSBorislav Petkov return -1;
1221f03e97dbSBorislav Petkov }
1222f03e97dbSBorislav Petkov
1223f03e97dbSBorislav Petkov return idx;
1224f03e97dbSBorislav Petkov }
1225f03e97dbSBorislav Petkov
p4_next_cntr(int thread,unsigned long * used_mask,struct p4_event_bind * bind)1226f03e97dbSBorislav Petkov static int p4_next_cntr(int thread, unsigned long *used_mask,
1227f03e97dbSBorislav Petkov struct p4_event_bind *bind)
1228f03e97dbSBorislav Petkov {
1229f03e97dbSBorislav Petkov int i, j;
1230f03e97dbSBorislav Petkov
1231f03e97dbSBorislav Petkov for (i = 0; i < P4_CNTR_LIMIT; i++) {
1232f03e97dbSBorislav Petkov j = bind->cntr[thread][i];
1233f03e97dbSBorislav Petkov if (j != -1 && !test_bit(j, used_mask))
1234f03e97dbSBorislav Petkov return j;
1235f03e97dbSBorislav Petkov }
1236f03e97dbSBorislav Petkov
1237f03e97dbSBorislav Petkov return -1;
1238f03e97dbSBorislav Petkov }
1239f03e97dbSBorislav Petkov
p4_pmu_schedule_events(struct cpu_hw_events * cpuc,int n,int * assign)1240f03e97dbSBorislav Petkov static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
1241f03e97dbSBorislav Petkov {
1242f03e97dbSBorislav Petkov unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1243f03e97dbSBorislav Petkov unsigned long escr_mask[BITS_TO_LONGS(P4_ESCR_MSR_TABLE_SIZE)];
1244f03e97dbSBorislav Petkov int cpu = smp_processor_id();
1245f03e97dbSBorislav Petkov struct hw_perf_event *hwc;
1246f03e97dbSBorislav Petkov struct p4_event_bind *bind;
1247f03e97dbSBorislav Petkov unsigned int i, thread, num;
1248f03e97dbSBorislav Petkov int cntr_idx, escr_idx;
1249f03e97dbSBorislav Petkov u64 config_alias;
1250f03e97dbSBorislav Petkov int pass;
1251f03e97dbSBorislav Petkov
1252f03e97dbSBorislav Petkov bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1253f03e97dbSBorislav Petkov bitmap_zero(escr_mask, P4_ESCR_MSR_TABLE_SIZE);
1254f03e97dbSBorislav Petkov
1255f03e97dbSBorislav Petkov for (i = 0, num = n; i < n; i++, num--) {
1256f03e97dbSBorislav Petkov
1257f03e97dbSBorislav Petkov hwc = &cpuc->event_list[i]->hw;
1258f03e97dbSBorislav Petkov thread = p4_ht_thread(cpu);
1259f03e97dbSBorislav Petkov pass = 0;
1260f03e97dbSBorislav Petkov
1261f03e97dbSBorislav Petkov again:
1262f03e97dbSBorislav Petkov /*
1263f03e97dbSBorislav Petkov * It's possible to hit a circular lock
1264f03e97dbSBorislav Petkov * between original and alternative events
1265f03e97dbSBorislav Petkov * if both are scheduled already.
1266f03e97dbSBorislav Petkov */
1267f03e97dbSBorislav Petkov if (pass > 2)
1268f03e97dbSBorislav Petkov goto done;
1269f03e97dbSBorislav Petkov
1270f03e97dbSBorislav Petkov bind = p4_config_get_bind(hwc->config);
1271f03e97dbSBorislav Petkov escr_idx = p4_get_escr_idx(bind->escr_msr[thread]);
1272f03e97dbSBorislav Petkov if (unlikely(escr_idx == -1))
1273f03e97dbSBorislav Petkov goto done;
1274f03e97dbSBorislav Petkov
1275f03e97dbSBorislav Petkov if (hwc->idx != -1 && !p4_should_swap_ts(hwc->config, cpu)) {
1276f03e97dbSBorislav Petkov cntr_idx = hwc->idx;
1277f03e97dbSBorislav Petkov if (assign)
1278f03e97dbSBorislav Petkov assign[i] = hwc->idx;
1279f03e97dbSBorislav Petkov goto reserve;
1280f03e97dbSBorislav Petkov }
1281f03e97dbSBorislav Petkov
1282f03e97dbSBorislav Petkov cntr_idx = p4_next_cntr(thread, used_mask, bind);
1283f03e97dbSBorislav Petkov if (cntr_idx == -1 || test_bit(escr_idx, escr_mask)) {
1284f03e97dbSBorislav Petkov /*
1285f03e97dbSBorislav Petkov * Check whether an event alias is still available.
1286f03e97dbSBorislav Petkov */
1287f03e97dbSBorislav Petkov config_alias = p4_get_alias_event(hwc->config);
1288f03e97dbSBorislav Petkov if (!config_alias)
1289f03e97dbSBorislav Petkov goto done;
1290f03e97dbSBorislav Petkov hwc->config = config_alias;
1291f03e97dbSBorislav Petkov pass++;
1292f03e97dbSBorislav Petkov goto again;
1293f03e97dbSBorislav Petkov }
1294f03e97dbSBorislav Petkov /*
1295f03e97dbSBorislav Petkov * Perf does test runs to see if a whole group can be assigned
1296a97673a1SIngo Molnar * together successfully. There can be multiple rounds of this.
1297f03e97dbSBorislav Petkov * Unfortunately, p4_pmu_swap_config_ts touches the hwc->config
1298f03e97dbSBorislav Petkov * bits, such that the next round of group assignments will
1299f03e97dbSBorislav Petkov * cause the above p4_should_swap_ts to pass instead of fail.
1300f03e97dbSBorislav Petkov * This leads to counters exclusive to thread0 being used by
1301f03e97dbSBorislav Petkov * thread1.
1302f03e97dbSBorislav Petkov *
1303f03e97dbSBorislav Petkov * Solve this with a cheap hack, reset the idx back to -1 to
1304f03e97dbSBorislav Petkov * force a new lookup (p4_next_cntr) to get the right counter
1305f03e97dbSBorislav Petkov * for the right thread.
1306f03e97dbSBorislav Petkov *
1307f03e97dbSBorislav Petkov * This probably doesn't comply with the general spirit of how
1308f03e97dbSBorislav Petkov * perf wants to work, but P4 is special. :-(
1309f03e97dbSBorislav Petkov */
1310f03e97dbSBorislav Petkov if (p4_should_swap_ts(hwc->config, cpu))
1311f03e97dbSBorislav Petkov hwc->idx = -1;
1312f03e97dbSBorislav Petkov p4_pmu_swap_config_ts(hwc, cpu);
1313f03e97dbSBorislav Petkov if (assign)
1314f03e97dbSBorislav Petkov assign[i] = cntr_idx;
1315f03e97dbSBorislav Petkov reserve:
1316f03e97dbSBorislav Petkov set_bit(cntr_idx, used_mask);
1317f03e97dbSBorislav Petkov set_bit(escr_idx, escr_mask);
1318f03e97dbSBorislav Petkov }
1319f03e97dbSBorislav Petkov
1320f03e97dbSBorislav Petkov done:
1321f03e97dbSBorislav Petkov return num ? -EINVAL : 0;
1322f03e97dbSBorislav Petkov }
1323f03e97dbSBorislav Petkov
1324f03e97dbSBorislav Petkov PMU_FORMAT_ATTR(cccr, "config:0-31" );
1325f03e97dbSBorislav Petkov PMU_FORMAT_ATTR(escr, "config:32-62");
1326f03e97dbSBorislav Petkov PMU_FORMAT_ATTR(ht, "config:63" );
1327f03e97dbSBorislav Petkov
1328f03e97dbSBorislav Petkov static struct attribute *intel_p4_formats_attr[] = {
1329f03e97dbSBorislav Petkov &format_attr_cccr.attr,
1330f03e97dbSBorislav Petkov &format_attr_escr.attr,
1331f03e97dbSBorislav Petkov &format_attr_ht.attr,
1332f03e97dbSBorislav Petkov NULL,
1333f03e97dbSBorislav Petkov };
1334f03e97dbSBorislav Petkov
1335f03e97dbSBorislav Petkov static __initconst const struct x86_pmu p4_pmu = {
1336f03e97dbSBorislav Petkov .name = "Netburst P4/Xeon",
1337f03e97dbSBorislav Petkov .handle_irq = p4_pmu_handle_irq,
1338f03e97dbSBorislav Petkov .disable_all = p4_pmu_disable_all,
1339f03e97dbSBorislav Petkov .enable_all = p4_pmu_enable_all,
1340f03e97dbSBorislav Petkov .enable = p4_pmu_enable_event,
1341f03e97dbSBorislav Petkov .disable = p4_pmu_disable_event,
1342dbf4e792SPeter Zijlstra
1343dbf4e792SPeter Zijlstra .set_period = p4_pmu_set_period,
1344dbf4e792SPeter Zijlstra
1345f03e97dbSBorislav Petkov .eventsel = MSR_P4_BPU_CCCR0,
1346f03e97dbSBorislav Petkov .perfctr = MSR_P4_BPU_PERFCTR0,
1347f03e97dbSBorislav Petkov .event_map = p4_pmu_event_map,
1348f03e97dbSBorislav Petkov .max_events = ARRAY_SIZE(p4_general_events),
1349f03e97dbSBorislav Petkov .get_event_constraints = x86_get_event_constraints,
1350f03e97dbSBorislav Petkov /*
1351f03e97dbSBorislav Petkov * IF HT disabled we may need to use all
1352163b0991SIngo Molnar * ARCH_P4_MAX_CCCR counters simultaneously
1353f03e97dbSBorislav Petkov * though leave it restricted at moment assuming
1354f03e97dbSBorislav Petkov * HT is on
1355f03e97dbSBorislav Petkov */
1356f03e97dbSBorislav Petkov .num_counters = ARCH_P4_MAX_CCCR,
1357f03e97dbSBorislav Petkov .apic = 1,
1358f03e97dbSBorislav Petkov .cntval_bits = ARCH_P4_CNTRVAL_BITS,
1359f03e97dbSBorislav Petkov .cntval_mask = ARCH_P4_CNTRVAL_MASK,
1360f03e97dbSBorislav Petkov .max_period = (1ULL << (ARCH_P4_CNTRVAL_BITS - 1)) - 1,
1361f03e97dbSBorislav Petkov .hw_config = p4_hw_config,
1362f03e97dbSBorislav Petkov .schedule_events = p4_pmu_schedule_events,
1363f03e97dbSBorislav Petkov
1364f03e97dbSBorislav Petkov .format_attrs = intel_p4_formats_attr,
1365f03e97dbSBorislav Petkov };
1366f03e97dbSBorislav Petkov
p4_pmu_init(void)1367f03e97dbSBorislav Petkov __init int p4_pmu_init(void)
1368f03e97dbSBorislav Petkov {
1369f03e97dbSBorislav Petkov unsigned int low, high;
1370f03e97dbSBorislav Petkov int i, reg;
1371f03e97dbSBorislav Petkov
1372f03e97dbSBorislav Petkov /* If we get stripped -- indexing fails */
1373f03e97dbSBorislav Petkov BUILD_BUG_ON(ARCH_P4_MAX_CCCR > INTEL_PMC_MAX_GENERIC);
1374f03e97dbSBorislav Petkov
1375f03e97dbSBorislav Petkov rdmsr(MSR_IA32_MISC_ENABLE, low, high);
1376f03e97dbSBorislav Petkov if (!(low & (1 << 7))) {
1377f03e97dbSBorislav Petkov pr_cont("unsupported Netburst CPU model %d ",
1378f03e97dbSBorislav Petkov boot_cpu_data.x86_model);
1379f03e97dbSBorislav Petkov return -ENODEV;
1380f03e97dbSBorislav Petkov }
1381f03e97dbSBorislav Petkov
1382f03e97dbSBorislav Petkov memcpy(hw_cache_event_ids, p4_hw_cache_event_ids,
1383f03e97dbSBorislav Petkov sizeof(hw_cache_event_ids));
1384f03e97dbSBorislav Petkov
1385f03e97dbSBorislav Petkov pr_cont("Netburst events, ");
1386f03e97dbSBorislav Petkov
1387f03e97dbSBorislav Petkov x86_pmu = p4_pmu;
1388f03e97dbSBorislav Petkov
1389f03e97dbSBorislav Petkov /*
1390f03e97dbSBorislav Petkov * Even though the counters are configured to interrupt a particular
1391f03e97dbSBorislav Petkov * logical processor when an overflow happens, testing has shown that
1392f03e97dbSBorislav Petkov * on kdump kernels (which uses a single cpu), thread1's counter
1393f03e97dbSBorislav Petkov * continues to run and will report an NMI on thread0. Due to the
1394f03e97dbSBorislav Petkov * overflow bug, this leads to a stream of unknown NMIs.
1395f03e97dbSBorislav Petkov *
1396f03e97dbSBorislav Petkov * Solve this by zero'ing out the registers to mimic a reset.
1397f03e97dbSBorislav Petkov */
1398f03e97dbSBorislav Petkov for (i = 0; i < x86_pmu.num_counters; i++) {
1399f03e97dbSBorislav Petkov reg = x86_pmu_config_addr(i);
1400f03e97dbSBorislav Petkov wrmsrl_safe(reg, 0ULL);
1401f03e97dbSBorislav Petkov }
1402f03e97dbSBorislav Petkov
1403f03e97dbSBorislav Petkov return 0;
1404f03e97dbSBorislav Petkov }
1405