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Searched refs:MSC (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-intel_th-devices-msc5 Description: (RW) Configure MSC buffer wrapping. 1 == wrapping enabled.
11 Description: (RW) Configure MSC operating mode:
27 Description: (RW) Configure MSC buffer size for "single" or "multi" modes.
42 Description: (RW) Trigger window switch for the MSC's buffer, in
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-msc-sm2s-ep1.dts13 model = "MSC SM2-MB-EP1 Carrier Board with SM2S-IMX8PLUS-QC6-14N0600E SoM";
/openbmc/qemu/hw/misc/
H A Dtrace-events217 tz_msc_reset(void) "TZ MSC: reset"
218 tz_msc_cfg_nonsec(int level) "TZ MSC: cfg_nonsec = %d"
219 tz_msc_cfg_sec_resp(int level) "TZ MSC: cfg_sec_resp = %d"
220 tz_msc_irq_clear(int level) "TZ MSC: int_clear = %d"
221 tz_msc_update_irq(int level) "TZ MSC: setting irq line to %d"
222 tz_msc_access_blocked(uint64_t offset) "TZ MSC: offset 0x%" PRIx64 " access blocked"
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/mcpp/files/
H A Dice-mcpp.patch45 + ! #define HOST_COMPILER MSC
/openbmc/u-boot/include/
H A DSA-1100.h1918 #define MSC /* Static memory Control reg. */ \ macro
1921 #define MSC0 (MSC [0]) /* Static memory Control reg. 0 */
1922 #define MSC1 (MSC [1]) /* Static memory Control reg. 1 */
/openbmc/linux/drivers/input/
H A Dinput.c1631 INPUT_DEV_CAP_ATTR(MSC, msc);
2280 INPUT_CLEANSE_BITMASK(dev, MSC, msc); in input_cleanse_bitmasks()
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi501 label = "MSC";
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc698 C(0xe353, MSC, RXY_a, MIE2,r1_32s, m2_32s, new, r1_32, mul, muls32)