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Searched refs:MPLL (Results 1 – 15 of 15) sorted by relevance

/openbmc/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c36 case MPLL: in s5pc100_get_pll_clk()
87 case MPLL: in s5pc110_get_pll_clk()
107 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk()
206 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1); in get_pclkd1()
236 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); in get_hclk_sys()
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c356 MPLL, enumerator
412 (selectplls[MPLL] << CPM_CPCCR_SEL_H0PLL_BIT) | in cpu_mux_select()
413 (selectplls[MPLL] << CPM_CPCCR_SEL_H2PLL_BIT); in cpu_mux_select()
455 { CPM_MSCCDR, MPLL, 30 }, in pll_init()
458 { CPM_GPUCDR, MPLL, 30 }, in pll_init()
461 { CPM_BCHCDR, MPLL, 30 }, in pll_init()
473 pll_init_one(MPLL, JZ4780_MPLL_M, JZ4780_MPLL_N, JZ4780_MPLL_OD); in pll_init()
477 cpu_mux_select(MPLL); in pll_init()
478 ddr_mux_select(MPLL); in pll_init()
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c195 case MPLL: in exynos4_get_pll_clk()
225 case MPLL: in exynos4x12_get_pll_clk()
256 case MPLL: in exynos5_get_pll_clk()
283 case MPLL: in exynos5_get_pll_clk()
314 case MPLL: in exynos542x_get_pll_clk()
667 sclk = get_pll_clk(MPLL); in exynos4_get_pwm_clk()
683 sclk = get_pll_clk(MPLL); in exynos4x12_get_pwm_clk()
713 sclk = get_pll_clk(MPLL); in exynos4_get_uart_clk()
759 sclk = get_pll_clk(MPLL); in exynos4x12_get_uart_clk()
795 sclk = get_pll_clk(MPLL); in exynos4_get_mmc_clk()
[all …]
/openbmc/linux/drivers/clk/mstar/
H A DKconfig10 bool "MStar MPLL driver"
15 Support for the MPLL PLL and dividers block present on
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmstar,msc313-mpll.yaml7 title: MStar/Sigmastar MSC313 MPLL
13 The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
H A Dmvebu-core-clock.txt38 3 = mpll (MPLL Clock)
/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dclk.h12 #define MPLL 1 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmicrochip,clock.h13 #define MPLL 2 macro
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dclk.h11 #define MPLL 1 macro
/openbmc/u-boot/arch/mips/mach-pic32/
H A Dcpu.c157 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL))); in soc_clk_dump()
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Damlogic,g12a-mdio-mux.yaml31 - description: SoC 50MHz MPLL
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos-fb.txt55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi45 /* derived from 532MHz MPLL */
137 /* derived from 532MHz MPLL */
185 /* derived from 532MHz MPLL */
/openbmc/u-boot/drivers/clk/
H A Dclk_pic32.c356 case MPLL: in pic32_get_rate()
/openbmc/linux/drivers/clk/ingenic/
H A Djz4780-cgu.c301 .pll = DEF_PLL(MPLL),