| /openbmc/linux/drivers/tty/ |
| H A D | amiserial.c | 83 int MCR; /* Modem control register */ member
492 info->MCR = 0; in startup()
494 info->MCR = SER_DTR | SER_RTS; in startup()
495 rtsdtr_ctrl(info->MCR); in startup()
554 info->MCR &= ~(SER_DTR|SER_RTS); in shutdown()
555 rtsdtr_ctrl(info->MCR); in shutdown()
860 info->MCR &= ~SER_RTS; in rs_throttle()
863 rtsdtr_ctrl(info->MCR); in rs_throttle()
882 info->MCR |= SER_RTS; in rs_unthrottle()
884 rtsdtr_ctrl(info->MCR); in rs_unthrottle()
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| H A D | mxser.c | 269 u8 MCR; /* Modem control register */ member
516 info->MCR |= UART_MCR_DTR; in mxser_set_baud()
517 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_set_baud()
519 info->MCR &= ~UART_MCR_DTR; in mxser_set_baud()
520 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_set_baud()
628 info->MCR &= ~UART_MCR_AFE; in mxser_change_speed()
633 info->MCR |= UART_MCR_AFE; in mxser_change_speed()
639 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_change_speed()
779 info->MCR = UART_MCR_DTR | UART_MCR_RTS; in mxser_activate()
780 outb(info->MCR, info->ioaddr + UART_MCR); in mxser_activate()
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| /openbmc/linux/arch/sh/boards/mach-hp6xx/ |
| H A D | pm.c | 29 #define MCR 0xffffff68 macro
64 mcr = __raw_readw(MCR); in pm_enter()
65 __raw_writew(mcr & ~MCR_RFSH, MCR); in pm_enter()
76 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR); in pm_enter()
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| /openbmc/linux/drivers/atm/ |
| H A D | idt77105.c | 135 PUT( walk->old_mcr ,MCR); in idt77105_restart_timer_func()
231 PRIV(dev)->old_mcr = GET(MCR); in idt77105_int()
237 ) & ~IDT77105_MCR_EIP, MCR); in idt77105_int()
296 PRIV(dev)->old_mcr = GET(MCR); in idt77105_start()
299 PUT(PRIV(dev)->old_mcr, MCR); in idt77105_start()
328 PUT( GET(MCR) & ~IDT77105_MCR_EIP, MCR ); in idt77105_stop()
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| /openbmc/linux/drivers/net/hamradio/ |
| H A D | baycom_ser_fdx.c | 98 #define MCR(iobase) (iobase+4) macro
290 outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr)); in ser12_interrupt()
292 outb(0x0d, MCR(dev->base_addr)); /* transmitter off */ in ser12_interrupt()
348 b1 = inb(MCR(iobase)); in ser12_check_uart()
349 outb(b1 | 0x10, MCR(iobase)); /* loopback mode */ in ser12_check_uart()
351 outb(0x1a, MCR(iobase)); in ser12_check_uart()
353 outb(b1, MCR(iobase)); /* restore old values */ in ser12_check_uart()
407 outb(0x0d, MCR(dev->base_addr)); in ser12_open()
450 outb(1, MCR(dev->base_addr)); in ser12_close()
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| H A D | baycom_ser_hdx.c | 84 #define MCR(iobase) (iobase+4) macro
193 outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr)); in ser12_tx()
339 outb(0x0d, MCR(dev->base_addr)); /* transmitter off */ in ser12_rx()
430 b1 = inb(MCR(iobase)); in ser12_check_uart()
431 outb(b1 | 0x10, MCR(iobase)); /* loopback mode */ in ser12_check_uart()
433 outb(0x1a, MCR(iobase)); in ser12_check_uart()
435 outb(b1, MCR(iobase)); /* restore old values */ in ser12_check_uart()
475 outb(0x0d, MCR(dev->base_addr)); in ser12_open()
509 outb(1, MCR(dev->base_addr)); in ser12_close()
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| H A D | yam.c | 155 #define MCR(iobase) (iobase+4) macro
302 outb(MCR_OUT1 | MCR_OUT2, MCR(iobase)); in fpga_reset()
305 outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase)); in fpga_reset()
321 outb(bit | MCR_OUT1 | MCR_OUT2, MCR(iobase)); in fpga_write()
470 outb(PTT_OFF, MCR(dev->base_addr)); in yam_set_uart()
501 b1 = inb(MCR(iobase)); in yam_check_uart()
502 outb(b1 | 0x10, MCR(iobase)); /* loopback mode */ in yam_check_uart()
504 outb(0x1a, MCR(iobase)); in yam_check_uart()
506 outb(b1, MCR(iobase)); /* restore old values */ in yam_check_uart()
572 outb(PTT_ON, MCR(dev->base_addr)); in ptt_on()
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| /openbmc/linux/arch/x86/boot/ |
| H A D | early_serial_console.c | 18 #define MCR 4 /* Modem control */ macro
34 outb(0x3, port + MCR); /* DTR + RTS */ in early_serial_init()
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| /openbmc/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7706.h | 28 #define MCR 0xffffff68 macro
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| H A D | cpu_sh7750.h | 55 #define MCR 0xFF800014 macro
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| /openbmc/linux/drivers/dma/ |
| H A D | txx9dmac.h | 96 TXX9_DMA_REG32(MCR); /* Master Control Register */
102 u32 MCR; member
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| H A D | txx9dmac.c | 651 mcr = dma_readl(ddev, MCR); in txx9dmac_tasklet()
676 dma_readl(ddev, MCR)); in txx9dmac_interrupt()
1077 dma_writel(ddev, MCR, 0); in txx9dmac_off()
1212 dma_writel(ddev, MCR, mcr); in txx9dmac_probe()
1254 dma_writel(ddev, MCR, mcr); in txx9dmac_resume_noirq()
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| /openbmc/linux/arch/x86/kernel/ |
| H A D | early_printk.c | 91 #define MCR 4 /* Modem control */ macro
137 serial_out(early_serial_base, MCR, 0x3); /* DTR + RTS */ in early_serial_hw_init()
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| /openbmc/linux/arch/arm/mach-orion5x/ |
| H A D | tsx09-common.c | 38 writel(0x00, UART1_REG(MCR)); in qnap_tsx09_power_off()
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| H A D | terastation_pro2-setup.c | 281 writel(0x00, UART1_REG(MCR)); in tsp2_power_off()
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| H A D | kurobox_pro-setup.c | 303 writel(0x00, UART1_REG(MCR)); in kurobox_pro_power_off()
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| /openbmc/linux/drivers/usb/serial/ |
| H A D | io_16654.h | 36 #define MCR 4 // Modem Control Register macro
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| /openbmc/linux/drivers/net/ethernet/smsc/ |
| H A D | smc9194.h | 93 #define MCR 10 macro
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| /openbmc/u-boot/board/ms7750se/ |
| H A D | lowlevel_init.S | 136 MCR_A: .long MCR
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| /openbmc/linux/drivers/power/reset/ |
| H A D | qnap-poweroff.c | 66 writel(0x00, UART1_REG(MCR)); in qnap_power_off()
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| /openbmc/u-boot/board/renesas/r2dplus/ |
| H A D | lowlevel_init.S | 107 MCR_A: .long MCR /* MCR Address */
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| /openbmc/u-boot/arch/arm/mach-omap2/ |
| H A D | lowlevel_init.S | 44 MCR p15, 4, R0, c1, c0, 0
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | vfpmacros.h | 26 MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | a32.decode | 540 # We decode MCR, MCR, MRRC and MCRR only, because for QEMU the
552 MCR .... 1110 ... 0 .... .... .... ... 1 .... @mcr
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| H A D | t32.decode | 701 # We decode MCR, MCR, MRRC and MCRR only, because for QEMU the
713 MCR 1110 1110 ... 0 .... .... .... ... 1 .... @mcr
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