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Searched refs:MASK (Results 1 – 25 of 36) sorted by relevance

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/openbmc/u-boot/board/micronas/vct/
H A Dgpio.c22 #define MASK(pin) (1 << ((pin) & 0x1F)) macro
46 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); in vct_gpio_dir()
48 clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); in vct_gpio_dir()
60 clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); in vct_gpio_set()
62 clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin)); in vct_gpio_set()
73 return ((value & MASK(pin)) ? 1 : 0); in vct_gpio_get()
/openbmc/qemu/include/qemu/
H A Dlog.h54 #define qemu_log_mask(MASK, FMT, ...) \ argument
56 if (unlikely(qemu_loglevel_mask(MASK))) { \
68 #define qemu_log_mask_and_addr(MASK, ADDR, FMT, ...) \ argument
70 if (unlikely(qemu_loglevel_mask(MASK)) && \
/openbmc/u-boot/test/lib/
H A Dstring.c19 #define MASK 0xA5 macro
83 ptr = memset(buf + offset, MASK, len); in lib_memset()
85 if (test_memset(uts, buf, MASK, offset, len)) { in lib_memset()
138 init_buffer(buf1, MASK); in lib_memcpy()
147 if (test_memmove(uts, buf2, MASK, offset1, in lib_memcpy()
/openbmc/qemu/include/hw/rtc/
H A Dxlnx-zynqmp-rtc.h67 FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1)
69 FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1)
71 FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1)
/openbmc/qemu/target/hexagon/mmvec/
H A Dmacros.h50 #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \ argument
53 if (MASK) { \
70 #define fGETQBITS(REG, WIDTH, MASK, BITNO) \ argument
71 ((MASK) & (REG.w[(BITNO) >> 5] >> ((BITNO) & 0x1f)))
96 #define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \ argument
99 REG.w[(BITNO) >> 5] &= ~((MASK) << ((BITNO) & 0x1f)); \
100 REG.w[(BITNO) >> 5] |= (((__TMP) & (MASK)) << ((BITNO) & 0x1f)); \
110 #define fV_AL_CHECK(EA, MASK) \ argument
111 if ((EA) & (MASK)) { \
295 #define fSTOREMMVQ(EA, SRC, MASK) \ argument
[all …]
/openbmc/qemu/hw/scsi/
H A Dvmw_pvscsi.h30 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro
372 #define PVSCSI_INTR_CMPL_MASK MASK(2)
376 #define PVSCSI_INTR_MSG_MASK (MASK(2) << 2)
378 #define PVSCSI_INTR_ALL_SUPPORTED MASK(4)
H A Dvmw_pvscsi.c160 m->txr_len_mask = MASK(txr_len_log2); in pvscsi_ring_init_data()
161 m->rxr_len_mask = MASK(rxr_len_log2); in pvscsi_ring_init_data()
201 m->msg_len_mask = MASK(len_log2); in pvscsi_ring_init_msg()
/openbmc/qemu/target/arm/tcg/
H A Diwmmxt_helper.c301 #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ argument
302 (TYPE) ((b >> SHR) & MASK)) ? (uint64_t) MASK : 0) << SHR)
307 #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ argument
308 (TYPE) ((b >> SHR) & MASK)) ? a : b) & ((uint64_t) MASK << SHR))
314 #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \ argument
315 OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
320 #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \ argument
321 OPER (TYPE) ((b >> SHR) & MASK)) & MASK) << SHR)
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dmacros.def41 ((MASK) & (REG.w[(BITNO)>>5] >> ((BITNO) & 0x1f))),
123 REG.w[(BITNO)>>5] &= ~((MASK) << ((BITNO) & 0x1f));
124 REG.w[(BITNO)>>5] |= (((__TMP) & (MASK)) << ((BITNO) & 0x1f));
203 if ((EA) & (MASK)) {
599 for (i = 0; i < fVECSIZE(); i++) maskvec.ub[i] = fGETQBIT(MASK,i);
606 fSTOREMMVQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK),
614 for (i = 0; i < fVECSIZE(); i++) maskvec.ub[i] = fGETQBIT(MASK,i);
622 fSTOREMMVNQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK),
660 for (i = 0; i < fVECSIZE(); i++) maskvec.ub[i] = fGETQBIT(MASK,i);
675 fSTOREMMVQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK);
[all …]
H A Dext.idef1711 #define VCMP(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \
1714 fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP ((VuV.SRC[i/WIDTH] CMP VvV.SRC[i/WIDTH]) ? MASK : 0)); \
1719 #define MMVEC_CMPGT(TYPE,TYPE2,TYPE3,DESCR,N,MASK,WIDTH,SRC) \
1721 VCMP(QdV, , , >, N, SRC, MASK, WIDTH)) \
1723 VCMP(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, >, N, SRC, MASK, WIDTH)) \
1725 VCMP(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, >, N, SRC, MASK, WIDTH)) \
1727 VCMP(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, >, N, SRC, MASK, WIDTH))
1729 #define MMVEC_CMP(TYPE,TYPE2,TYPE3,DESCR,N,MASK, WIDTH, SRC)\
1730 MMVEC_CMPGT(TYPE,TYPE2,TYPE3,DESCR,N,MASK,WIDTH,SRC) \
1732 VCMP(QdV, , , ==, N, SRC, MASK, WIDTH)) \
[all …]
/openbmc/qemu/target/ppc/
H A Dinternal.h57 FUNC_MASK(MASK, target_ulong, 64, UINT64_MAX);
59 FUNC_MASK(MASK, target_ulong, 32, UINT32_MAX);
/openbmc/u-boot/include/
H A Dlattice.h130 #define MASK 0x15 /* The following data stream is used as mask. */ macro
H A Dsym53c8xx.h529 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) macro
/openbmc/u-boot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg144 ; MASK: | mask |
148 ;MASK = 0x00FF0000
/openbmc/qemu/target/arm/
H A Dhyp_gdbstub.c174 wp.wcr = FIELD_DP64(wp.wcr, DBGWCR, MASK, bits); in insert_hw_watchpoint()
/openbmc/qemu/hw/net/can/
H A Dtrace-events6 xlnx_can_filter_mask_pre_write(uint8_t filter_num, uint32_t value) "Filter%d MASK: 0x%08x"
/openbmc/qemu/target/hexagon/imported/
H A Dcompare.idef582 fHIDE(size4u_t TLBHI; size4u_t TLBLO; size4u_t MASK; size4u_t SIZE;)
583 MASK = 0x07ffffff;
587 MASK &= (0xffffffff << 2*SIZE);
588 PdV = f8BITSOF(fGETBIT(31,TLBHI) && ((TLBHI & MASK) == (RtV & MASK)));
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A DKconfig82 hex "MASK for setting SCCR register"
/openbmc/u-boot/doc/
H A DREADME.Heterogeneous-SoCs30 MASK, similar to the code written for PowerPC
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-multimedia/libmad/libmad/
H A DCVE-2017-8374.patch596 value += MASK(bitcache, cachesz, linbits);
624 value += MASK(bitcache, cachesz, linbits);
691 quad = &table[MASK(bitcache, cachesz, 4)];
693 MASK(bitcache, cachesz, quad->ptr.bits)];
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc246 /* COMPARE LOGICAL CHARACTERS UNDER MASK */
402 /* INSERT CHARACTERS UNDER MASK */
413 /* INSERT PROGRAM MASK */
812 /* SET PROGRAM MASK */
863 /* STORE CHARACTERS UNDER MASK */
970 /* TEST UNDER MASK */
1026 /* VECTOR GENERATE BYTE MASK */
1028 /* VECTOR GENERATE MASK */
1220 /* VECTOR ELEMENT ROTATE AND INSERT UNDER MASK */
1263 /* VECTOR TEST UNDER MASK */
[all …]
/openbmc/qemu/include/hw/
H A Dregisterfields.h167 enum { name ## _ ## MASK = MAKE_64BIT_MASK(shift, length)};
/openbmc/u-boot/drivers/fpga/
H A Divm_core.c445 case MASK: in ispVMMemManager()
1202 case MASK: in ispVMDataCode()
/openbmc/qemu/target/loongarch/tcg/
H A Dvec_helper.c2326 #define VFRSTP(NAME, BIT, MASK, E) \ argument
2337 m = Vk->E(i * ofs) & MASK; \
3165 #define XVINSVE0(NAME, E, MASK) \ argument
3170 Vd->E(imm & MASK) = Vj->E(0); \
3176 #define XVPICKVE(NAME, E, BIT, MASK) \ argument
3184 Vd->E(0) = Vj->E(imm & MASK); \
3474 #define VEXTRINS(NAME, BIT, E, MASK) \ argument
3483 ins = (imm >> 4) & MASK; \
3484 extr = imm & MASK; \
/openbmc/qemu/tests/qtest/libqos/
H A Dahci.c1261 #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK))) in ahci_command_wait() argument

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