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Searched refs:M1 (Results 1 – 25 of 47) sorted by relevance

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/openbmc/u-boot/board/intel/cherryhill/
H A Dcherryhill.c20 GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
23 GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
26 GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
29 GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
32 GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
35 GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
38 GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
41 GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
44 GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
47 GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
[all …]
/openbmc/u-boot/board/ti/dra7xx/
H A Dmux_data.h43 {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
44 {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
45 {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
46 {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
47 {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
48 {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
49 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
50 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
51 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
52 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
[all …]
/openbmc/u-boot/board/compulab/cl-som-am57x/
H A Dmux.c53 {GPMC_A13, (M1 | PIN_INPUT) }, /* GPMC_A13.QSPI1_RTCLK */
54 {GPMC_A18, (M1 | PIN_INPUT) }, /* GPMC_A18.QSPI1_SCLK */
55 {GPMC_A16, (M1 | PIN_INPUT) }, /* GPMC_A16.QSPI1_D0 */
56 {GPMC_A17, (M1 | PIN_INPUT) }, /* GPMC_A17.QSPI1_D1 */
57 {GPMC_CS2, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_CS2.QSPI1_CS0 */
68 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A19.MMC2_DAT4 */
69 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A20.MMC2_DAT5 */
70 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A21.MMC2_DAT6 */
71 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A22.MMC2_DAT7 */
72 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* GPMC_A23.MMC2_CLK */
[all …]
/openbmc/u-boot/board/ti/sdp4430/
H A Dsdp4430_mux_data.h16 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
17 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
18 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
19 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
20 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
21 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
22 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
23 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
24 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
25 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
/openbmc/u-boot/board/amazon/kc1/
H A Dkc1.h21 { GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */
22 { GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */
23 { GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */
24 { GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */
25 { GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */
26 { GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */
27 { GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */
28 { GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */
29 { GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */
30 { GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */
/openbmc/u-boot/board/ti/panda/
H A Dpanda_mux_data.h17 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
18 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
19 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
20 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
21 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
22 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
23 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
24 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
25 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
26 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
/openbmc/u-boot/board/ti/am57xx/
H A Dmux_data.h50 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
51 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
52 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
53 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
54 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
55 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
56 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
57 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
58 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
59 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv6m/
H A Dtune-cortexm1.inc2 # Tune Settings for Cortex-M1
6 TUNEVALID[cortexm1] = "Enable Cortex-M1 specific processor optimizations"
/openbmc/u-boot/board/ti/beagle/
H A Dbeagle.h110 MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
111 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
205 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
206 MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
207 MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
208 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
218 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
219 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
220 MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
221 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
[all …]
/openbmc/u-boot/board/technexion/tao3530/
H A Dtao3530.h212 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) \
213 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) \
214 MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) \
215 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) \
216 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)) \
218 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)) \
219 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) \
221 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) \
285 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M1)) \
286 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M1)) \
[all …]
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dtie-asm.h76 rsr.M1 \at1 // MAC16 option
131 wsr.M1 \at1 // MAC16 option
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dtie-asm.h48 rsr \at2, M1
91 wsr \at2, M1
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dtie-asm.h85 rsr \at1, M1 // MAC16 option
150 wsr \at1, M1 // MAC16 option
/openbmc/u-boot/board/overo/
H A Dovero.h140 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
141 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
142 MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
143 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
H A Dcommon.c163 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
164 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
165 MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
168 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
169 MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
170 MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
171 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
/openbmc/u-boot/board/nokia/rx51/
H A Drx51.h106 MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*nDMA_REQ2*/\
107 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*nDMA_REQ3*/\
201 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
202 MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
203 MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
204 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
214 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT*/\
215 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG*/\
216 MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY*/\
217 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
/openbmc/u-boot/board/corscience/tricorder/
H A Dtricorder.h207 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*GPIO_152*/\
208 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*GPIO_153*/\
209 MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*GPIO_154*/\
210 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*GPIO_155*/\
274 MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTU | EN | M1)) /*SPI3_SIMO*/\
275 MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTU | EN | M1)) /*SPI3_SOMI*/\
276 MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CS0*/\
277 MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CLK*/\
281 MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CS1*/\
/openbmc/u-boot/board/compulab/cm_t3517/
H A Dmux.c187 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ in set_muxconf_regs()
188 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ in set_muxconf_regs()
189 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ in set_muxconf_regs()
190 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ in set_muxconf_regs()
/openbmc/u-boot/board/lg/sniper/
H A Dsniper.h102 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* dsi_dx0 */ \
103 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* dsi_dy0 */ \
104 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* dsi_dx1 */ \
105 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* dsi_dy1 */ \
106 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* dsi_dx2 */ \
107 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* dsi_dy2 */ \
/openbmc/u-boot/board/compulab/cm_t35/
H A Dcm_t35.c314 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ in cm_t3x_set_common_muxconf()
315 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ in cm_t3x_set_common_muxconf()
316 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ in cm_t3x_set_common_muxconf()
317 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ in cm_t3x_set_common_muxconf()
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dmux_omap5.h40 #define M1 1 macro
H A Dmux_dra7xx.h30 #define M1 1 macro
/openbmc/u-boot/arch/x86/include/asm/arch-braswell/
H A Dgpio.h15 M1, enumerator
/openbmc/u-boot/arch/arm/include/asm/arch-omap4/
H A Dmux_omap4.h48 #define M1 1 macro
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-h3-nanopi-m1.dts46 model = "FriendlyArm NanoPi M1";

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