Home
last modified time | relevance | path

Searched refs:LPC (Results 1 – 25 of 97) sorted by relevance

1234

/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed-lpc.yaml8 title: Aspeed Low Pin Count (LPC) Bus Controller
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
26 * An LPC Host Interface Controller manages functions exposed to the host such
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
34 Additionally the state of the LPC controller influences the pinmux
66 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
127 bytes written by the Host to the targeted LPC I/O pots.
145 description: The LPC I/O ports to snoop
[all …]
/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
51 | PCH-LPC | | Devices | | Devices |
64 PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
82 | PCH-LPC | | Devices | | Devices |
129 PCH-LPC::
157 - PCH-LPC：即《龙芯7A1000桥片用户手册》第24.3节所描述的“LPC中断”。
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dst,stih407-lpc1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Drtc-st-lpc.txt1 STMicroelectronics Low Power Controller (LPC) - RTC
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dst_lpc_wdt.txt1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
48 | PCH-LPC | | Devices | | Devices |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
80 | PCH-LPC | | Devices | | Devices |
127 PCH-LPC::
159 - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
/openbmc/linux/drivers/soc/aspeed/
H A DKconfig8 tristate "ASPEED LPC firmware cycle control"
13 Control LPC firmware cycle mappings through ioctl()s. The driver
15 host LPC read/write region can be buffered.
18 tristate "ASPEED LPC snoop support"
23 Provides a driver to control the LPC snoop interface which
25 the host to an arbitrary LPC I/O port.
/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md6 host and BMC over the LPC bus on ASPEED BMC platforms.
52 **LPC Bus: Low Pin Count Bus**
57 **LPC FW: LPC Firmware Cycles**
94 ## MCTP over LPC Transport
106 1. Write the packet to the LPC FW window
118 3. Read the MCTP packet from the LPC FW window
156 ### LPC FW Window
285 the ability to send and receive packets on the LPC bus.
350 #### LPC Window Ownership and Synchronisation
371 ### LPC Binding Operation
[all …]
/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-driver-aspeed-vuart5 will appear on the host <-> BMC LPC bus.
13 the UART will appear on the host <-> BMC LPC bus.
21 host via the BMC LPC bus.
/openbmc/linux/drivers/net/ethernet/nxp/
H A DKconfig3 tristate "NXP ethernet MAC on LPC devices"
9 some NXP LPC devices. You can safely enable this option for LPC32xx
/openbmc/phosphor-mboxd/Documentation/
H A Dmboxd.md30 mboxd_lpc.c - Contains the functions for controlling the LPC bus mapping
45 currently suspended and the LPC bus maps the flash
48 currently suspended and the LPC bus maps the flash
51 currently suspended and the LPC bus maps the reserved
54 currently suspended and the LPC bus maps the reserved
91 it at the correct LPC offset for that windows location and the requested flash
98 this window and the host pointed at its location on the LPC bus.
132 After initilisation, the daemon points the LPC mapping to the actual flash
169 SIGHUP - Clear the window cache and point the LPC bus mapping back to
180 active window has been closed, points the LPC bus mapping back to flash, clears
/openbmc/hiomapd/Documentation/
H A Dmboxd.md29 lpc.c - Contains the functions for controlling the LPC bus mapping
44 currently suspended and the LPC bus maps the flash
47 currently suspended and the LPC bus maps the flash
50 currently suspended and the LPC bus maps the reserved
53 currently suspended and the LPC bus maps the reserved
90 it at the correct LPC offset for that windows location and the requested flash
97 this window and the host pointed at its location on the LPC bus.
131 After initilisation, the daemon points the LPC mapping to the actual flash
168 SIGHUP - Clear the window cache and point the LPC bus mapping back to
179 the active window has been closed, points the LPC bus mapping back to flash,
H A Dprotocol.md33 flash data in the LPC firmware space, communicated via functions in the LPC IO
140 1. The [ASPEED BMC LPC Mailbox transport](#mailbox-transport)
271 as the LPC mailbox transport.
686 | LPC FW Offset | Blocks | 2 | 0 | 0 | q |
711 | LPC FW Address | Blocks | 2 | 0 | 0 | q |
739 | LPC FW Address | Blocks | 2 | 0 | 0 | q |
752 LPC bus address is always given from the start of the LPC address space - that
888 | LPC FW Offset | Blocks | 2 | 0 | 0 | q |
913 | LPC FW Address | Blocks | 2 | 0 | 0 | q |
941 | LPC FW Address | Blocks | 2 | 0 | 0 | q |
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ipmi/
H A Daspeed,ast2400-kcs-bmc.yaml14 interfaces on the LPC bus for in-band IPMI communication with their host.
48 The host CPU LPC IO data and status addresses for the device. For most
57 A 2-cell property expressing the LPC SerIRQ number and the interrupt
67 description: The LPC channel number in the controller
/openbmc/openbmc-test-automation/oem/nuvoton/
H A Dtest_ipmi_flash.robot31 Get LPC SHM Address
37 Get LPC SHM Address
49 Get LPC SHM Address
63 Get LPC SHM Address
75 Get LPC SHM Address
102 Get LPC SHM Address
103 [Documentation] Get Mapped Address of LPC hare Memory.
/openbmc/linux/drivers/mcb/
H A DKconfig33 tristate "LPC (non PCI) based MCB carrier"
37 This is a MCB carrier on a LPC or non PCI device.
/openbmc/linux/Documentation/devicetree/bindings/arm/hisilicon/
H A Dlow-pin-count.yaml13 Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
17 LPC device node.
/openbmc/openbmc/meta-openpower/recipes-phosphor/host/aspeed-lpc-ctrl/
H A Dpnorboot.service2 Description=ASPEED LPC boot from PNOR
/openbmc/phosphor-host-postd/
H A Dlpcsnoop.service.in2 Description=LPC Snoop Daemon
H A DREADME.md1 # LPC Snoop Broadcast Daemon
/openbmc/u-boot/arch/arm/mach-aspeed/
H A DKconfig23 which is enabled by support of LPC and eSPI peripherals.
32 which is enabled by support of LPC and eSPI peripherals.
45 which is enabled by support of LPC and eSPI peripherals.
/openbmc/u-boot/doc/device-tree-bindings/misc/
H A Dintel-lpc.txt1 Intel LPC Device Binding
14 the LPC device
/openbmc/phosphor-ipmi-flash/
H A Dmeson.build54 # Enable LPC and PCI for tests only.
59 'Invalid configuration enabling both PCI and LPC.')
104 summary(option_key, option_value, section : 'Enabled LPC Features')
/openbmc/docs/designs/
H A Dfirmware-update-via-blobs.md25 1. IPMI over LPC
27 1. LPC Memory-Mapped Region
51 the P2A bridge and what region to use or whether to turn on the LPC memory map
223 #### LPC Sequence
226 1. WriteMeta (specify region information from host for LPC)
231 1. WriteMeta (LPC Region)
232 1. SessionStat (verify LPC config)
280 lpc = (1 << 10), /* Expect to send contents over LPC bridge. */
324 ##### If LPC
471 aimed at LPC which needs to be told the memory address so it can configure the
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-quark/acpi/
H A Dlpc.asl6 /* Intel LPC Bus Device - 0:1f.0 */
102 /* LPC device: Resource consumption */

1234