Lines Matching refs:LPC

1 # Management Component Transport Protocol (MCTP) LPC Transport Binding Specification for ASPEED BMC…
6 host and BMC over the LPC bus on ASPEED BMC platforms.
17 2. Intel (R) Low Pin Count (LPC) Interface Specification 1.1,
52 ### LPC Bus: Low Pin Count Bus
57 ### LPC FW: LPC Firmware Cycles
59 LPC firmware cycles allow separate boot BIOS firmware memory cycles and
60 application memory cycles with respect to the LPC bus. The ASPEED BMCs allow
61 remapping of the LPC firmware cycles onto arbitrary regions of the BMC's
94 ## MCTP over LPC Transport
101 - A window of the LPC FW address space, where reads and writes are forwarded to
106 1. Write the packet to the LPC FW window
107    - The BMC will perform writes by writing to the memory backing the LPC window
108    - The host will perform writes by writing to the LPC bus, at predefined
118 3. Read the MCTP packet from the LPC FW window
125 1. The LPC IO address and Serial IRQ parameters of the KCS device
126 2. The concrete location of the control region in the LPC FW address space
131 remote side, that a packet is ready to be transferred through the LPC FW
156 ### LPC FW Window
158 The window of BMC-memory-backed LPC FW address space has a predefined format,
166 transmit and receive areas. These offsets are relative to the start of the LPC
276 - Not extend beyond the window allocated to MCTP in the LPC FW address space
285 the ability to send and receive packets on the LPC bus.
350 #### LPC Window Ownership and Synchronisation
352 Because the LPC FW window is shared between the host and the BMC we need strict
371 ### LPC Binding Operation
441 - An LPC KCS device exposed by a [binding-specific kernel driver][mctp-driver]
452 From the host side, the LPC Firmware and KCS IO cycles are driven by
454 implementing the driver hooks for direct access to the LPC devices.
485 ### Using the AST2500 LPC Mailbox