Lines Matching refs:LPC

33 flash data in the LPC firmware space, communicated via functions in the LPC IO
52 2. Remapping of LPC Firmware cycles onto the AHB (LPC2AHB bridge)
64 The core concept of the protocol moves access away from the naive routing of LPC
66 on servicing the LPC firmware cycles from reserved system memory. As the memory
75 The original transport for the protocol was the ASPEED BMC LPC mailbox
88 which adjusts the mapping of the LPC firmware space as requested and returns a
109 …nd)                             | ✓   | ✓   | ✓   | Reset the state of the LPC firmware space, clo…
140 1. The [ASPEED BMC LPC Mailbox transport](#mailbox-transport)
146 design is limited by the most constrained transport - the LPC mailbox
182 the associated LPC firmware cycles to write the regions into the erased state.
251 active window and the host must not access the LPC firmware space until a window
259 The host must not access an LPC address other than that which is contained by
271 as the LPC mailbox transport.
480 Requests the BMC return the LPC firmware space to a state ready for host
686 | LPC FW Offset | Blocks | 2    | 0   | 0   | q   |
711 | LPC FW Address | Blocks | 2    | 0   | 0   | q   |
739 | LPC FW Address | Blocks | 2    | 0   | 0   | q   |
752 LPC bus address is always given from the start of the LPC address space - that
849 Closes the active window. Any further access to the LPC bus address specified to
888 | LPC FW Offset | Blocks | 2    | 0   | 0   | q   |
913 | LPC FW Address | Blocks | 2    | 0   | 0   | q   |
941 | LPC FW Address | Blocks | 2    | 0   | 0   | q   |
954 LPC bus address is always given from the start of the LPC address space - that
1056 The BMC has no method for intercepting writes that occur over the LPC bus. The