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/openbmc/qemu/tests/qemu-iotests/
H A D271.out9 L2 entry #0: 0x8000000000050000 0000000000000001
11 L2 entry #0: 0x8000000000050000 0000000000000003
13 L2 entry #0: 0x8000000000050000 0000000000000007
15 L2 entry #0: 0x8000000000050000 000000000000000f
17 L2 entry #0: 0x8000000000050000 000000000000007f
19 L2 entry #0: 0x8000000000050000 00000000000003ff
21 L2 entry #0: 0x8000000000050000 00000000000103ff
23 L2 entry #0: 0x8000000000050000 00000000800103ff
24 L2 entry #1: 0x8000000000060000 0000000000000003
26 L2 entry #0: 0x8000000000050000 00000002800103fd
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H A D092.out10 == Invalid L2 table size ==
12 qemu-io: can't open device TEST_DIR/t.qcow: L2 table size must be between 512 and 64k
13 qemu-io: can't open device TEST_DIR/t.qcow: L2 table size must be between 512 and 64k
14 qemu-io: can't open device TEST_DIR/t.qcow: L2 table size must be between 512 and 64k
15 qemu-io: can't open device TEST_DIR/t.qcow: L2 table size must be between 512 and 64k
H A D026.out.nocache17 qemu-io: Failed to flush the L2 table cache: Input/output error
24 qemu-io: Failed to flush the L2 table cache: Input/output error
41 qemu-io: Failed to flush the L2 table cache: No space left on device
48 qemu-io: Failed to flush the L2 table cache: No space left on device
131 qemu-io: Failed to flush the L2 table cache: Input/output error
139 qemu-io: Failed to flush the L2 table cache: Input/output error
159 qemu-io: Failed to flush the L2 table cache: No space left on device
167 qemu-io: Failed to flush the L2 table cache: No space left on device
185 qemu-io: Failed to flush the L2 table cache: Input/output error
192 qemu-io: Failed to flush the L2 table cache: Input/output error
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H A D026.out17 qemu-io: Failed to flush the L2 table cache: Input/output error
24 qemu-io: Failed to flush the L2 table cache: Input/output error
41 qemu-io: Failed to flush the L2 table cache: No space left on device
48 qemu-io: Failed to flush the L2 table cache: No space left on device
129 qemu-io: Failed to flush the L2 table cache: Input/output error
136 qemu-io: Failed to flush the L2 table cache: Input/output error
153 qemu-io: Failed to flush the L2 table cache: No space left on device
160 qemu-io: Failed to flush the L2 table cache: No space left on device
177 qemu-io: Failed to flush the L2 table cache: Input/output error
184 qemu-io: Failed to flush the L2 table cache: Input/output error
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H A D060.out3 === Testing L2 reference into L1 ===
59 === Testing cluster data reference into inactive L2 table ===
75 qcow2: Marking image as corrupt: Preventing invalid write on metadata (overlaps with inactive L2 ta…
110 qcow2: Marking image as corrupt: Preventing invalid write on metadata (overlaps with active L2 tabl…
129 qcow2: Marking image as corrupt: L2 table offset 0x42a00 unaligned (L1 index: 0); further corruptio…
134 qcow2: Marking image as corrupt: L2 table offset 0x42a00 unaligned (L1 index: 0); further corruptio…
137 === Testing unaligned L2 entry ===
142 …g image as corrupt: Cluster allocation offset 0x52a00 unaligned (L2 offset: 0x40000, L2 index: 0);…
150 …g image as corrupt: Cluster allocation offset 0x52a00 unaligned (L2 offset: 0x40000, L2 index: 0);…
173 qcow2: Image is corrupt: Cluster allocation offset 0x52a00 unaligned (L2 offset: 0x40000, L2 index:…
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/openbmc/qemu/tests/unit/
H A Dtest-hbitmap.c20 #define L2 (BITS_PER_LONG * L1) macro
21 #define L3 (BITS_PER_LONG * L2)
245 hbitmap_test_check(data, L2 - 1); in test_hbitmap_iter_partial()
246 hbitmap_test_check(data, L2); in test_hbitmap_iter_partial()
247 hbitmap_test_check(data, L2 + 1); in test_hbitmap_iter_partial()
248 hbitmap_test_check(data, L2 + L1); in test_hbitmap_iter_partial()
249 hbitmap_test_check(data, L2 + L1 * 2 - 1); in test_hbitmap_iter_partial()
250 hbitmap_test_check(data, L2 * 2 - 1); in test_hbitmap_iter_partial()
251 hbitmap_test_check(data, L2 * 2); in test_hbitmap_iter_partial()
252 hbitmap_test_check(data, L2 * 2 + 1); in test_hbitmap_iter_partial()
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/openbmc/linux/arch/mips/cavium-octeon/
H A DKconfig31 bool "Lock often used kernel code in the L2"
34 Enable locking parts of the kernel into the L2 cache.
37 bool "Lock the TLB handler in L2"
41 Lock the low level TLB fast path into L2.
44 bool "Lock the exception handler in L2"
48 Lock the low level exception handler into L2.
51 bool "Lock the interrupt handler in L2"
55 Lock the low level interrupt handler into L2.
58 bool "Lock the 2nd level interrupt handler in L2"
62 Lock the 2nd level interrupt handler in L2.
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/openbmc/qemu/docs/
H A Dqcow2-cache.txt1 qcow2 L2/refcount cache configuration
15 This document attempts to give an overview of the L2 and refcount
36 The L2 tables
40 called the L1 and L2 tables.
45 There can be many L2 tables, depending on how much space has been
48 corresponding L2 table to find out where that data is located. Since
50 an L2 cache in memory to speed up disk access.
52 The size of the L2 cache can be configured, and setting the right
61 L1/L2 tables described above.
74 aforementioned L2 cache, and its size can also be configured.
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/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dfreescale-l2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
42 - reg : Address and size of L2 cache controller registers
43 - cache-size : Size of the entire L2 cache
44 - interrupts : Error interrupt of L2 controller
45 - cache-line-size : Size of L2 cache lines
49 L2: l2-cache-controller@20000 {
53 cache-size = <0x40000>; // L2,256K
/openbmc/linux/arch/arc/kernel/
H A Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
156 ; -L2 interrupts L1 (before L1 ISR could run)
159 ; Returns from L2 context fine
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
165 ; L2 interrupting L1 implies both L2 and L1 active
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
209 ; out of the L2 interrupt context (drop to pure kernel mode) and jump
320 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
335 ; However the context returning might not have taken L2 intr itself
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/openbmc/linux/security/apparmor/include/
H A Dlabel.h163 #define next_comb(I, L1, L2) \ argument
166 if ((I).j >= (L2)->size) { \
174 #define label_for_each_comb(I, L1, L2, P1, P2) \ argument
176 ((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]); \
177 (I) = next_comb(I, L1, L2))
179 #define fn_for_each_comb(L1, L2, P1, P2, FN) \ argument
183 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \
243 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \ argument
247 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
253 #define fn_for_each_in_merge(L1, L2, P, FN) \ argument
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H A Dperms.h183 #define xcheck_ns_labels(L1, L2, FN, args...) \ argument
186 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
190 #define xcheck_labels_profiles(L1, L2, FN, args...) \ argument
191 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
193 #define xcheck_labels(L1, L2, P, FN1, FN2) \ argument
194 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts25 next-level-cache = <&L2>;
44 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
82 next-level-cache = <&L2>;
135 L2: cache-controller { label
/openbmc/linux/Documentation/virt/kvm/x86/
H A Drunning-nested-guests.rst14 | L2 | | L2 |
36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
45 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
49 L1, and L2) for all architectures; and will largely focus on
139 .. note:: If you suspect your L2 (i.e. nested guest) is running slower,
191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
193 "savevm"/"loadvm") until the L2 guest shuts down. Attempting to migrate
194 or save-and-load an L1 guest while an L2 guest is running will result in
199 actually running L2 guests, is expected to function normally even on AMD
202 Migrating an L2 guest is always expected to succeed, so all the following
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/openbmc/qemu/docs/interop/
H A Dqed_spec.txt9 …e. A regular cluster may be a '''data cluster''', an '''L2''', or an '''L1 table'''. L1 and L2 t…
20 uint32_t table_size; /* for L1 and L2 tables, in clusters */
73 | L2 table | ... | L2 table |
85 L1, L2, and data cluster offsets must be aligned to header.cluster_size. The following offsets hav…
87 ===L2 table offsets===
88 * 0 - unallocated. The L2 table is not yet allocated.
96 ===Unallocated L2 tables and data clusters===
99 Writes to an unallocated area cause a new data clusters to be allocated, and a new L2 table if that…
114 | L1 index | L2 index | byte offset |
134 …t is an inconsistency to have a cluster referenced more than once by L1 or L2 tables. A cluster h…
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/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-dt.txt33 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
59 next-level-cache = <&L2>;
/openbmc/phosphor-inventory-manager/
H A Dutils.hpp150 template <typename L1, typename L2, typename R1, typename R2>
151 bool operator()(const std::pair<L1, L2>& l, in operator ()()
168 template <typename L1, typename L2, typename R>
169 bool operator()(const std::pair<L1, L2>& l, const R& r) const in operator ()()
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca9.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
164 L2: cache-controller@1e00a000 { label
225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
H A Darm-realview-eb-a9mp.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
H A Darm-realview-eb-11mp.dts46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
60 next-level-cache = <&L2>;
67 next-level-cache = <&L2>;
/openbmc/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_common.c519 IAVF_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
520 IAVF_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
521 IAVF_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
524 IAVF_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
525 IAVF_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
528 IAVF_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
529 IAVF_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
530 IAVF_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
531 IAVF_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
532 IAVF_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
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/openbmc/linux/Documentation/locking/
H A Dlockdep-design.rst22 dependency can be understood as lock order, where L1 -> L2 suggests that
23 a task is attempting to acquire L2 while holding L1. From lockdep's
24 perspective, the two locks (L1 and L2) are not necessarily related; that
145 <L1> -> <L2>
146 <L2> -> <L1>
521 L1 -> L2
523 , which means lockdep has seen L1 held before L2 held in the same context at runtime.
524 And in deadlock detection, we care whether we could get blocked on L2 with L1 held,
525 IOW, whether there is a locker L3 that L1 blocks L3 and L2 gets blocked by L3. So
526 we only care about 1) what L1 blocks and 2) what blocks L2. As a result, we can combine
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/openbmc/linux/drivers/cache/
H A DKconfig5 bool "Andes Technology AX45MP L2 Cache controller"
9 Support for the L2 cache controller on Andes Technology AX45MP platforms.
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610.dtsi8 next-level-cache = <&L2>;
12 L2: cache-controller@40006000 { label
/openbmc/linux/arch/powerpc/perf/
H A Disa207-common.c226 ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
260 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
262 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM); in isa207_find_source()
269 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
271 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0); in isa207_find_source()

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