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Searched refs:L1I (Results 1 – 25 of 32) sorted by relevance

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/openbmc/linux/arch/alpha/kernel/
H A Dsetup.c1281 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1288 L1I = CSHAPE(8*1024, 5, 1); in determine_cpu_caches()
1290 L1I = CSHAPE(16*1024, 5, 1); in determine_cpu_caches()
1291 L1D = L1I; in determine_cpu_caches()
1312 L1I = L1D = CSHAPE(8*1024, 5, 1); in determine_cpu_caches()
1327 L1I = L1D = CSHAPE(8*1024, 5, 1); in determine_cpu_caches()
1352 L1I = CSHAPE(16*1024, 6, 1); in determine_cpu_caches()
1355 L1I = CSHAPE(32*1024, 6, 2); in determine_cpu_caches()
1379 L1I = L1D = CSHAPE(64*1024, 6, 2); in determine_cpu_caches()
1386 L1I = L1D = CSHAPE(64*1024, 6, 2); in determine_cpu_caches()
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dperf_event_v7.c184 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
185 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
234 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
273 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
274 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
279 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
280 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
323 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
324 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
372 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
[all …]
H A Dperf_event_v6.c101 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
164 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
/openbmc/linux/drivers/perf/
H A Driscv_pmu_sbi.c146 [C(L1I)] = {
149 C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
151 C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
155 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
157 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
161 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
163 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}},
H A Darm_pmuv3.c64 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
65 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
129 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
130 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
/openbmc/linux/arch/powerpc/perf/
H A De6500-pmu.c42 [C(L1I)] = {
H A De500-pmu.c44 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
H A Dpower10-pmu.c373 [C(L1I)] = {
474 [C(L1I)] = {
H A Dmpc7450-pmu.c371 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
H A Dgeneric-compat-pmu.c200 [ C(L1I) ] = {
H A Dpower8-pmu.c281 [ C(L1I) ] = {
H A Dppc970-pmu.c444 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
H A Dpower7-pmu.c345 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
H A Dpower6-pmu.c493 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
H A Dpower9-pmu.c352 [ C(L1I) ] = {
H A Dpower5-pmu.c573 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
/openbmc/linux/arch/mips/kernel/
H A Dperf_event_mipsxx.c1026 [C(L1I)] = {
1107 [C(L1I)] = {
1176 [C(L1I)] = {
1220 [C(L1I)] = {
1276 [C(L1I)] = {
1340 [C(L1I)] = {
1393 [C(L1I)] = {
1444 [C(L1I)] = {
/openbmc/linux/arch/x86/events/zhaoxin/
H A Dcore.c65 [C(L1I)] = {
169 [C(L1I)] = {
/openbmc/linux/arch/x86/events/intel/
H A Dp6.c42 [ C(L1I ) ] = {
H A Dknc.c45 [ C(L1I ) ] = {
H A Dcore.c490 [ C(L1I ) ] = {
641 [ C(L1I ) ] = {
869 [ C(L1I ) ] = {
1025 [ C(L1I ) ] = {
1177 [ C(L1I ) ] = {
1179 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1180 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1360 [ C(L1I ) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1363 [ C(RESULT_MISS) ] = 0x0280, /* L1I
[all...]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dperf_event.c131 [ C(L1I) ] = {
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dperf_event.c106 [ C(L1I) ] = {
/openbmc/linux/arch/sparc/kernel/
H A Dperf_event.c235 [C(L1I)] = {
373 [C(L1I)] = {
508 [C(L1I)] = {
645 [C(L1I)] = {
/openbmc/linux/arch/x86/events/amd/
H A Dcore.c45 [ C(L1I ) ] = {
149 [C(L1I)] = {

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