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Searched refs:ISR (Results 1 – 15 of 15) sorted by relevance

/openbmc/qemu/hw/char/
H A Dstm32l4x5_usart.c114 REG32(ISR, 0x1C)
116 FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */
117 FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */
118 FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */
119 FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */
120 FIELD(ISR, SBKF, 18, 1) /* Send break flag */
121 FIELD(ISR, CMF, 17, 1) /* Character match flag */
122 FIELD(ISR, BUSY, 16, 1) /* Busy flag */
123 FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */
124 FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */
[all …]
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_usart-test.c39 REG32(ISR, 0x1C)
40 FIELD(ISR, REACK, 22, 1)
41 FIELD(ISR, TEACK, 21, 1)
42 FIELD(ISR, TXE, 7, 1)
43 FIELD(ISR, RXNE, 5, 1)
44 FIELD(ISR, ORE, 3, 1)
/openbmc/u-boot/arch/x86/include/asm/
H A Di8259.h14 #define ISR 0x0 /* In-Service Register */ macro
/openbmc/qemu/hw/net/can/
H A Dtrace-events2 xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
12 xlnx_canfd_update_irq(char *path, uint32_t isr, uint32_t ier, uint32_t irq) "%s: ISR: 0x%08x IER: 0…
/openbmc/u-boot/drivers/net/
H A Dax88180.c565 OUTW (dev, INW (dev, ISR), ISR); in ax88180_init()
580 ISR_Status = INW (dev, ISR); in ax88180_recv()
584 OUTW (dev, ISR_Status, ISR); in ax88180_recv()
600 ISR_Status = INW (dev, ISR); in ax88180_recv()
H A Dax88180.h138 #define ISR (CMD_BASE + 0x0008) macro
/openbmc/qemu/tests/tcg/multiarch/
H A Dtest-aes-main.c.inc152 verify(&rounds[i].start, &t, "ISB+ISR");
166 verify(&rounds[i - 1].after_sr, &t, "ISB+ISR+AK+IMC");
178 verify(&rounds[i - 1].after_sr, &t, "ISB+ISR+IMC+AK");
/openbmc/qemu/docs/specs/
H A Dedu.rst75 status register. This needs to be done from the ISR to stop
H A Drocker.rst150 Software should install the Interrupt Service Routine (ISR) before any ports
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S107 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
117 ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout
133 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
/openbmc/u-boot/arch/arm/include/asm/arch-imx/
H A Dimx-regs.h124 #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) macro
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S257 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
266 ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout
282 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c678 REG32(ISR, 0x800)
679 FIELD(ISR, ADDR_DECODE_ERR, 0, 1)
/openbmc/qemu/hw/intc/
H A Dtrace-events90 aspeed_intc_all_isr_done(const char *s, int inpin_idx) "%s: All source ISR execution are done: %d"
95 aspeed_intc_all_isr_done_bit(const char *s, int inpin_idx, int bit) "%s: All source ISR execution a…
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex992 isr & uint64 & Register ISR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\
1165 isr\_el1 & uint64 & Register ISR (EL1).\\