xref: /openbmc/u-boot/arch/x86/include/asm/i8259.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2002
4  * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
5  */
6 
7 /* i8259.h i8259 PIC Registers */
8 
9 #ifndef _ASMI386_I8259_H_
10 #define _ASMI386_I8959_H_
11 
12 /* PIC I/O mapped registers */
13 #define IRR		0x0	/* Interrupt Request Register */
14 #define ISR		0x0	/* In-Service Register */
15 #define ICW1		0x0	/* Initialization Control Word 1 */
16 #define OCW2		0x0	/* Operation Control Word 2 */
17 #define OCW3		0x0	/* Operation Control Word 3 */
18 #define ICW2		0x1	/* Initialization Control Word 2 */
19 #define ICW3		0x1	/* Initialization Control Word 3 */
20 #define ICW4		0x1	/* Initialization Control Word 4 */
21 #define IMR		0x1	/* Interrupt Mask Register */
22 
23 /* IRR, IMR, ISR and ICW3 bits */
24 #define	IR7		0x80	/* IR7 */
25 #define	IR6		0x40	/* IR6 */
26 #define	IR5		0x20	/* IR5 */
27 #define	IR4		0x10	/* IR4 */
28 #define	IR3		0x08	/* IR3 */
29 #define	IR2		0x04	/* IR2 */
30 #define	IR1		0x02	/* IR1 */
31 #define	IR0		0x01	/* IR0 */
32 
33 /* SEOI bits */
34 #define	SEOI_IR7	0x07	/* IR7 */
35 #define	SEOI_IR6	0x06	/* IR6 */
36 #define	SEOI_IR5	0x05	/* IR5 */
37 #define	SEOI_IR4	0x04	/* IR4 */
38 #define	SEOI_IR3	0x03	/* IR3 */
39 #define	SEOI_IR2	0x02	/* IR2 */
40 #define	SEOI_IR1	0x01	/* IR1 */
41 #define	SEOI_IR0	0x00	/* IR0 */
42 
43 /* OCW2 bits */
44 #define OCW2_RCLR	0x00	/* Rotate/clear */
45 #define OCW2_NEOI	0x20	/* Non specific EOI */
46 #define OCW2_NOP	0x40	/* NOP */
47 #define OCW2_SEOI	0x60	/* Specific EOI */
48 #define OCW2_RSET	0x80	/* Rotate/set */
49 #define OCW2_REOI	0xa0	/* Rotate on non specific EOI */
50 #define OCW2_PSET	0xc0	/* Priority Set Command */
51 #define OCW2_RSEOI	0xe0	/* Rotate on specific EOI */
52 
53 /* ICW1 bits */
54 #define ICW1_SEL	0x10	/* Select ICW1 */
55 #define ICW1_LTIM	0x08	/* Level-Triggered Interrupt Mode */
56 #define ICW1_ADI	0x04	/* Address Interval */
57 #define ICW1_SNGL	0x02	/* Single PIC */
58 #define ICW1_EICW4	0x01	/* Expect initilization ICW4 */
59 
60 /*
61  * ICW2 is the starting vector number
62  *
63  * ICW2 is bit-mask of present slaves for a master device,
64  * or the slave ID for a slave device
65  */
66 
67 /* ICW4 bits */
68 #define ICW4_AEOI	0x02	/* Automatic EOI Mode */
69 #define ICW4_PM		0x01	/* Microprocessor Mode */
70 
71 #define ELCR1		0x4d0
72 #define ELCR2		0x4d1
73 
74 int i8259_init(void);
75 
76 #endif /* _ASMI386_I8959_H_ */
77