| /openbmc/linux/drivers/media/pci/intel/ |
| H A D | Kconfig | 7 tristate "Intel IPU Bridge"
10 The IPU bridge is a helper library for Intel IPU drivers to
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| /openbmc/linux/drivers/gpu/drm/ingenic/ |
| H A D | Kconfig | 23 bool "IPU support for Ingenic SoCs"
25 Choose this option to enable support for the IPU found in Ingenic SoCs.
27 The Image Processing Unit (IPU) will appear as a second primary plane.
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| /openbmc/u-boot/board/aristainetos/ |
| H A D | axi.cfg | 16 /* enable AXI cache for VDOA/VPU/IPU */
19 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/u-boot/board/advantech/dms-ba16/ |
| H A D | clocks.cfg | 10 /* enable AXI cache for VDOA/VPU/IPU */
12 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/u-boot/board/tqc/tqma6/ |
| H A D | clocks.cfg | 19 /* enable AXI cache for VDOA/VPU/IPU */
21 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/u-boot/board/boundary/nitrogen6x/ |
| H A D | clocks.cfg | 25 /* enable AXI cache for VDOA/VPU/IPU */
27 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/u-boot/board/toradex/apalis_imx6/ |
| H A D | clocks.cfg | 26 /* enable AXI cache for VDOA/VPU/IPU */
28 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/u-boot/board/toradex/colibri_imx6/ |
| H A D | clocks.cfg | 26 /* enable AXI cache for VDOA/VPU/IPU */
28 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/linux/Documentation/devicetree/bindings/display/imx/ |
| H A D | fsl-imx-drm.txt | 5 IPU or other display interface nodes that comprise the graphics subsystem.
10 of IPU devices
36 - fsl,prg: phandle to prg node associated with this IPU instance
127 Port 0 is the input port connected to the IPU display interface,
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| H A D | ldb.txt | 14 multiplexer in the front to select any of the four IPU display
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | imx.txt | 14 sensor interface ports of IPU devices
34 to the i.MX IPU CSIs.
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| /openbmc/u-boot/board/freescale/mx6qarm2/ |
| H A D | imximage.cfg | 204 /* enable AXI cache for VDOA/VPU/IPU */
206 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
331 /* enable AXI cache for VDOA/VPU/IPU */
333 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | dra74-ipu-dsp-common.dtsi | 3 * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms
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| H A D | dra7-ipu-dsp-common.dtsi | 3 * Common IPU and DSP data for TI DRA7xx/AM57xx platforms
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| /openbmc/linux/drivers/gpu/ipu-v3/ |
| H A D | Kconfig | 11 Processing Unit. This option only enables IPU base support.
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| /openbmc/linux/drivers/media/pci/intel/ivsc/ |
| H A D | Kconfig | 15 Unit(IPU) driver of Intel.
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| /openbmc/u-boot/board/ge/bx50v3/ |
| H A D | bx50v3.cfg | 135 /* enable AXI cache for VDOA/VPU/IPU */
137 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/u-boot/board/tbs/tbs2910/ |
| H A D | tbs2910.cfg | 26 /* enable AXI cache for VDOA/VPU/IPU */
28 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
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| /openbmc/u-boot/board/seco/mx6quq7/ |
| H A D | mx6quq7-2g.cfg | 166 /* enable AXI cache for VDOA/VPU/IPU */
169 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/ |
| H A D | mediatek,ipu.txt | 1 Mediatek IPU controller
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| /openbmc/u-boot/board/barco/titanium/ |
| H A D | imximage.cfg | 162 /* enable AXI cache for VDOA/VPU/IPU */
164 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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| /openbmc/linux/Documentation/userspace-api/media/drivers/ |
| H A D | imx-uapi.rst | 34 this happens, the IPU triggers a mechanism to re-establish vertical
46 While the reason for this observation isn't known (the IPU dummy
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx53-qsb-common.dtsi | 332 fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */
333 fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */
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| /openbmc/linux/Documentation/admin-guide/media/ |
| H A D | imx.rst | 9 The Freescale i.MX5/6 contains an Image Processing Unit (IPU), which
13 For image capture, the IPU contains the following internal subunits:
43 The IPU time-shares the IC task operations. The time-slice granularity
63 In addition to the IPU internal subunits, there are also two units
64 outside the IPU that are also involved in video capture on i.MX:
148 is a "CSI-2 to IPU gasket". The gasket acts as a demultiplexer of the
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-fs-f2fs | 54 0x00 DISABLE disable IPU(=default option in LFS mode)
61 flash storages. IPU will be triggered only if the
64 0x20 ASYNC do IPU given by asynchronous write requests
65 0x40 NOCACHE disable IPU bio cache
66 0x80 HONOR_OPU_WRITE use OPU write prior to IPU write if inode has
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