1efdbd734SRob HerringFreescale i.MX DRM master device
2efdbd734SRob Herring================================
3efdbd734SRob Herring
4efdbd734SRob HerringThe freescale i.MX DRM master device is a virtual device needed to list all
5efdbd734SRob HerringIPU or other display interface nodes that comprise the graphics subsystem.
6efdbd734SRob Herring
7efdbd734SRob HerringRequired properties:
8efdbd734SRob Herring- compatible: Should be "fsl,imx-display-subsystem"
9efdbd734SRob Herring- ports: Should contain a list of phandles pointing to display interface ports
10efdbd734SRob Herring  of IPU devices
11efdbd734SRob Herring
12efdbd734SRob Herringexample:
13efdbd734SRob Herring
14efdbd734SRob Herringdisplay-subsystem {
15*d7a3fd7fSCengiz Can	compatible = "fsl,imx-display-subsystem";
16efdbd734SRob Herring	ports = <&ipu_di0>;
17efdbd734SRob Herring};
18efdbd734SRob Herring
19efdbd734SRob Herring
20efdbd734SRob HerringFreescale i.MX IPUv3
21efdbd734SRob Herring====================
22efdbd734SRob Herring
23efdbd734SRob HerringRequired properties:
240d6c9a42SLucas Stach- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
250d6c9a42SLucas Stach  - imx51
260d6c9a42SLucas Stach  - imx53
270d6c9a42SLucas Stach  - imx6q
280d6c9a42SLucas Stach  - imx6qp
29efdbd734SRob Herring- reg: should be register base and length as documented in the
30efdbd734SRob Herring  datasheet
31efdbd734SRob Herring- interrupts: Should contain sync interrupt and error interrupt,
32efdbd734SRob Herring  in this order.
33efdbd734SRob Herring- resets: phandle pointing to the system reset controller and
34efdbd734SRob Herring          reset line index, see reset/fsl,imx-src.txt for details
350d6c9a42SLucas StachAdditional required properties for fsl,imx6qp-ipu:
360d6c9a42SLucas Stach- fsl,prg: phandle to prg node associated with this IPU instance
37efdbd734SRob HerringOptional properties:
38efdbd734SRob Herring- port@[0-3]: Port nodes with endpoint definitions as defined in
39efdbd734SRob Herring  Documentation/devicetree/bindings/media/video-interfaces.txt.
40efdbd734SRob Herring  Ports 0 and 1 should correspond to CSI0 and CSI1,
41efdbd734SRob Herring  ports 2 and 3 should correspond to DI0 and DI1, respectively.
42efdbd734SRob Herring
43efdbd734SRob Herringexample:
44efdbd734SRob Herring
45efdbd734SRob Herringipu: ipu@18000000 {
46efdbd734SRob Herring	#address-cells = <1>;
47efdbd734SRob Herring	#size-cells = <0>;
48efdbd734SRob Herring	compatible = "fsl,imx53-ipu";
49efdbd734SRob Herring	reg = <0x18000000 0x080000000>;
50efdbd734SRob Herring	interrupts = <11 10>;
51efdbd734SRob Herring	resets = <&src 2>;
52efdbd734SRob Herring
53efdbd734SRob Herring	ipu_di0: port@2 {
54efdbd734SRob Herring		reg = <2>;
55efdbd734SRob Herring
56efdbd734SRob Herring		ipu_di0_disp0: endpoint {
57efdbd734SRob Herring			remote-endpoint = <&display_in>;
58efdbd734SRob Herring		};
59efdbd734SRob Herring	};
60efdbd734SRob Herring};
61efdbd734SRob Herring
62dcddda56SLucas StachFreescale i.MX PRE (Prefetch Resolve Engine)
63dcddda56SLucas Stach============================================
64dcddda56SLucas Stach
65dcddda56SLucas StachRequired properties:
66dcddda56SLucas Stach- compatible: should be "fsl,imx6qp-pre"
67dcddda56SLucas Stach- reg: should be register base and length as documented in the
68dcddda56SLucas Stach  datasheet
69dcddda56SLucas Stach- clocks : phandle to the PRE axi clock input, as described
70dcddda56SLucas Stach  in Documentation/devicetree/bindings/clock/clock-bindings.txt and
719ac2a661SMauro Carvalho Chehab  Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
72dcddda56SLucas Stach- clock-names: should be "axi"
73dcddda56SLucas Stach- interrupts: should contain the PRE interrupt
74dcddda56SLucas Stach- fsl,iram: phandle pointing to the mmio-sram device node, that should be
75dcddda56SLucas Stach  used for the PRE SRAM double buffer.
76dcddda56SLucas Stach
77dcddda56SLucas Stachexample:
78dcddda56SLucas Stach
79dcddda56SLucas Stachpre@21c8000 {
80dcddda56SLucas Stach	compatible = "fsl,imx6qp-pre";
81dcddda56SLucas Stach	reg = <0x021c8000 0x1000>;
82dcddda56SLucas Stach	interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
83dcddda56SLucas Stach	clocks = <&clks IMX6QDL_CLK_PRE0>;
84dcddda56SLucas Stach	clock-names = "axi";
85dcddda56SLucas Stach	fsl,iram = <&ocram2>;
86dcddda56SLucas Stach};
87dcddda56SLucas Stach
8863863d43SLucas StachFreescale i.MX PRG (Prefetch Resolve Gasket)
8963863d43SLucas Stach============================================
9063863d43SLucas Stach
9163863d43SLucas StachRequired properties:
9263863d43SLucas Stach- compatible: should be "fsl,imx6qp-prg"
9363863d43SLucas Stach- reg: should be register base and length as documented in the
9463863d43SLucas Stach  datasheet
9563863d43SLucas Stach- clocks : phandles to the PRG ipg and axi clock inputs, as described
9663863d43SLucas Stach  in Documentation/devicetree/bindings/clock/clock-bindings.txt and
979ac2a661SMauro Carvalho Chehab  Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
9863863d43SLucas Stach- clock-names: should be "ipg" and "axi"
9963863d43SLucas Stach- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
10063863d43SLucas Stach  PRE as the first entry and the muxable PREs following.
10163863d43SLucas Stach
10263863d43SLucas Stachexample:
10363863d43SLucas Stach
10463863d43SLucas Stachprg@21cc000 {
10563863d43SLucas Stach	compatible = "fsl,imx6qp-prg";
10663863d43SLucas Stach	reg = <0x021cc000 0x1000>;
10763863d43SLucas Stach	clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
10863863d43SLucas Stach		 <&clks IMX6QDL_CLK_PRG0_AXI>;
10963863d43SLucas Stach	clock-names = "ipg", "axi";
11063863d43SLucas Stach	fsl,pres = <&pre1>, <&pre2>, <&pre3>;
11163863d43SLucas Stach};
11263863d43SLucas Stach
113efdbd734SRob HerringParallel display support
114efdbd734SRob Herring========================
115efdbd734SRob Herring
116efdbd734SRob HerringRequired properties:
117efdbd734SRob Herring- compatible: Should be "fsl,imx-parallel-display"
118efdbd734SRob HerringOptional properties:
11913d5aa80SPhilipp Zabel- interface-pix-fmt: How this display is connected to the
120efdbd734SRob Herring  display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
121efdbd734SRob Herring  and "lvds666".
122efdbd734SRob Herring- edid: verbatim EDID data block describing attached display.
123efdbd734SRob Herring- ddc: phandle describing the i2c bus handling the display data
124efdbd734SRob Herring  channel
125efdbd734SRob Herring- port@[0-1]: Port nodes with endpoint definitions as defined in
126efdbd734SRob Herring  Documentation/devicetree/bindings/media/video-interfaces.txt.
127efdbd734SRob Herring  Port 0 is the input port connected to the IPU display interface,
128efdbd734SRob Herring  port 1 is the output port connected to a panel.
129efdbd734SRob Herring
130efdbd734SRob Herringexample:
131efdbd734SRob Herring
132dbfdd153SMarco Franchidisp0 {
133efdbd734SRob Herring	compatible = "fsl,imx-parallel-display";
134efdbd734SRob Herring	edid = [edid-data];
135efdbd734SRob Herring	interface-pix-fmt = "rgb24";
136efdbd734SRob Herring
137efdbd734SRob Herring	port@0 {
138efdbd734SRob Herring		reg = <0>;
139efdbd734SRob Herring
140efdbd734SRob Herring		display_in: endpoint {
141efdbd734SRob Herring			remote-endpoint = <&ipu_di0_disp0>;
142efdbd734SRob Herring		};
143efdbd734SRob Herring	};
144efdbd734SRob Herring
145efdbd734SRob Herring	port@1 {
146efdbd734SRob Herring		reg = <1>;
147efdbd734SRob Herring
148efdbd734SRob Herring		display_out: endpoint {
149efdbd734SRob Herring			remote-endpoint = <&panel_in>;
150efdbd734SRob Herring		};
151efdbd734SRob Herring	};
152efdbd734SRob Herring};
153efdbd734SRob Herring
154efdbd734SRob Herringpanel {
155efdbd734SRob Herring	...
156efdbd734SRob Herring
157efdbd734SRob Herring	port {
158efdbd734SRob Herring		panel_in: endpoint {
159efdbd734SRob Herring			remote-endpoint = <&display_out>;
160efdbd734SRob Herring		};
161efdbd734SRob Herring	};
162efdbd734SRob Herring};
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