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Searched refs:IP0_31_28 (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c49 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
160 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0… macro
266 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
413 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
414 PINMUX_IPSR_GPSR(IP0_31_28, A7),
415 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
2260 IP0_31_28
H A Dpfc-r8a77995.c79 #define GPSR1_0 F_(DU_DB0, IP0_31_28)
208 #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_… macro
358 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
550 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
551 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
552 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
2262 IP0_31_28
H A Dpfc-r8a7795.c101 #define GPSR2_1 F_(IRQ1, IP0_31_28)
219 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
410 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
636 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
637 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
638 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
639 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
640 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
H A Dpfc-r8a7796.c107 #define GPSR2_1 F_(IRQ1, IP0_31_28)
225 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
416 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
639 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
640 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
641 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
642 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
645 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
H A Dpfc-r8a77990.c105 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
196 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0)… macro
368 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
550 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
551 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
552 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
553 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
4932 IP0_31_28
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c60 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
171 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0… macro
276 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
421 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
422 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
423 PINMUX_IPSR_GPSR(IP0_31_28, A7),
424 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
2233 IP0_31_28
H A Dpfc-r8a77980.c62 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
205 #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0)… macro
326 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
494 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
495 PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
496 PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
497 PINMUX_IPSR_GPSR(IP0_31_28, A7),
498 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
2687 IP0_31_28
H A Dpfc-r8a77995.c88 #define GPSR1_0 F_(DU_DB0, IP0_31_28)
217 #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_… macro
367 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
560 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
561 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
562 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
2674 IP0_31_28
H A Dpfc-r8a77965.c148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
687 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
688 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
689 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
690 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
693 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
H A Dpfc-r8a77951.c143 #define GPSR2_1 F_(IRQ1, IP0_31_28)
261 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
452 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
681 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
682 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
683 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
684 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
685 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
686 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
687 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
H A Dpfc-r8a7796.c148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANF… macro
457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
686 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
687 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
688 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
689 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
690 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
691 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
[all …]
H A Dpfc-r8a77990.c130 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
221 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0)… macro
393 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
580 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
581 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
582 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
583 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
4789 IP0_31_28
H A Dpfc-r8a77470.c573 PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
574 PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
575 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),