| /openbmc/linux/arch/arm/mach-rpc/include/mach/ |
| H A D | hardware.h | 34 #define IO_BASE IOMEM(0xe0000000) macro
46 #define VIDC_BASE (IO_BASE + 0x00400000)
47 #define EXPMASK_BASE (IO_BASE + 0x00360000)
48 #define ECARD_IOC4_BASE (IO_BASE + 0x00270000)
49 #define ECARD_IOC_BASE (IO_BASE + 0x00240000)
50 #define IOMD_BASE (IO_BASE + 0x00200000)
51 #define IOC_BASE (IO_BASE + 0x00200000)
52 #define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000)
53 #define FLOPPYDMA_BASE (IO_BASE + 0x0002a000)
54 #define PCIO_BASE (IO_BASE + 0x00010000)
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| /openbmc/linux/arch/m68k/include/asm/ |
| H A D | apollohw.h | 52 #define IO_BASE 0x80000000 macro
77 #define sio01 ((*(volatile struct SCN2681 *)(IO_BASE + sio01_physaddr)))
78 #define sio23 ((*(volatile struct SCN2681 *)(IO_BASE + sio23_physaddr)))
79 #define rtc (((volatile struct mc146818 *)(IO_BASE + rtc_physaddr)))
80 #define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
81 #define pica (IO_BASE + pica_physaddr)
82 #define picb (IO_BASE + picb_physaddr)
83 #define apollo_timer (IO_BASE + timer_physaddr)
84 #define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
86 …ne isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
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| /openbmc/linux/arch/mips/include/asm/txx9/ |
| H A D | rbtx4927.h | 37 #define RBTX4927_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
38 #define RBTX4927_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
39 #define RBTX4927_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
40 #define RBTX4927_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
41 #define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
42 #define RBTX4927_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f002)
43 #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
44 #define RBTX4927_BRAMRTC_BASE (IO_BASE + TXX9_CE(2) + 0x00010000)
45 #define RBTX4927_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
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| /openbmc/qemu/hw/m68k/ |
| H A D | q800.c | 64 #define IO_BASE 0x50000000 macro
69 #define VIA_BASE (IO_BASE + 0x00000)
70 #define SONIC_PROM_BASE (IO_BASE + 0x08000)
71 #define SONIC_BASE (IO_BASE + 0x0a000)
72 #define SCC_BASE (IO_BASE + 0x0c020)
73 #define DJMEMC_BASE (IO_BASE + 0x0e000)
74 #define ESP_BASE (IO_BASE + 0x10000)
75 #define ESP_PDMA (IO_BASE + 0x10100)
76 #define ASC_BASE (IO_BASE + 0x14000)
150 addr |= IO_BASE; in macio_alias_read()
[all …]
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| /openbmc/linux/arch/mips/include/asm/mach-generic/ |
| H A D | spaces.h | 34 #ifndef IO_BASE
35 #define IO_BASE _AC(0xa0000000, UL) macro
60 #ifndef IO_BASE
61 #define IO_BASE _AC(0x9000000000000000, UL) macro
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| /openbmc/u-boot/arch/mips/include/asm/mach-generic/ |
| H A D | spaces.h | 25 #ifndef IO_BASE
26 #define IO_BASE _AC(0xa0000000, UL) macro
59 #ifndef IO_BASE
60 #define IO_BASE _AC(0x9000000000000000, UL) macro
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| /openbmc/u-boot/drivers/pch/ |
| H A D | pch9.c | 11 #define IO_BASE 0x4c macro
59 dm_pci_read_config32(dev, IO_BASE, &base); in pch9_get_io_base()
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| /openbmc/linux/arch/loongarch/include/asm/ |
| H A D | addrspace.h | 27 #ifndef IO_BASE
28 #define IO_BASE CSR_DMW0_BASE macro
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| /openbmc/linux/arch/mips/txx9/rbtx4927/ |
| H A D | setup.c | 290 .start = RBTX4927_BRAMRTC_BASE - IO_BASE, in toshiba_rbtx4927_rtc_init()
291 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1, in toshiba_rbtx4927_rtc_init()
353 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); in rbtx4927_device_init()
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| /openbmc/linux/arch/mips/txx9/generic/ |
| H A D | pci.c | 197 set_io_port_base(IO_BASE + pcic->mem_resource[1].start); in txx9_alloc_pci_controller()
200 pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start; in txx9_alloc_pci_controller()
204 io_base - (mips_io_port_base - IO_BASE); in txx9_alloc_pci_controller()
205 pcic->io_offset = io_base - (mips_io_port_base - IO_BASE); in txx9_alloc_pci_controller()
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| /openbmc/linux/arch/mips/include/asm/mach-cavium-octeon/ |
| H A D | spaces.h | 17 #define IO_BASE _AC(0x8000000000000000, UL) macro
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| /openbmc/linux/arch/mips/include/asm/mach-ip27/ |
| H A D | spaces.h | 22 #define IO_BASE _AC(0x9200000000000000, UL) macro
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| /openbmc/linux/arch/mips/include/asm/sibyte/ |
| H A D | sb1250.h | 52 #define IOADDR(a) ((void __iomem *)(IO_BASE + (a)))
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| /openbmc/linux/arch/mips/mm/ |
| H A D | ioremap64.c | 9 u64 base = (flags == _CACHE_UNCACHED ? IO_BASE : UNCAC_BASE); in ioremap_prot()
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| /openbmc/linux/drivers/watchdog/ |
| H A D | sb_wdog.c | 92 static char __iomem *kern_dog = (char __iomem *)(IO_BASE + (A_SCD_WDOG_CFG_0));
93 static char __iomem *user_dog = (char __iomem *)(IO_BASE + (A_SCD_WDOG_CFG_1));
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| /openbmc/linux/arch/arm/mach-versatile/ |
| H A D | integrator-hardware.h | 14 #define IO_BASE 0xF0000000 // VA of IO macro
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
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| /openbmc/linux/arch/mips/sgi-ip27/ |
| H A D | ip27-init.c | 134 set_io_port_base(IO_BASE); in plat_mem_setup()
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| /openbmc/linux/arch/mips/sgi-ip30/ |
| H A D | ip30-setup.c | 137 set_io_port_base(IO_BASE); in plat_mem_setup()
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| H A D | ip30-xtalk.c | 21 #define IP30_RAW_SWIN_BASE(widget) (IO_BASE + IP30_SWIN_BASE(widget))
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| /openbmc/linux/arch/arm/mach-rpc/ |
| H A D | riscpc.c | 74 .virtual = (u32)IO_BASE,
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| /openbmc/linux/arch/mips/include/asm/sgi/ |
| H A D | heart.h | 24 #define HEART_XKPHYS_BASE ((void *)(IO_BASE | 0x000000000ff00000ULL))
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| /openbmc/linux/arch/arm/mach-lpc32xx/ |
| H A D | lpc32xx.h | 706 #define IO_BASE 0xF0000000 macro
712 IO_BASE)
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | dnfb.c | 132 .smem_start = (FRAME_BUFFER_START + IO_BASE),
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| /openbmc/linux/arch/mips/include/asm/sn/ |
| H A D | addrs.h | 62 #define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n))
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| /openbmc/linux/arch/mips/kernel/ |
| H A D | setup.c | 702 if (UNCAC_BASE != IO_BASE) in resource_init()
|