| /openbmc/linux/drivers/i3c/master/mipi-i3c-hci/ |
| H A D | pio.c | 217 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_cleanup()
252 if (!(pio_reg_read(INTR_STATUS) & STAT_RX_THLD)) in hci_pio_do_rx()
318 if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD)) in hci_pio_do_tx()
337 if (!(pio_reg_read(INTR_STATUS) & STAT_TX_THLD)) in hci_pio_do_tx()
479 (pio_reg_read(INTR_STATUS) & STAT_RESP_READY)) { in hci_pio_process_resp()
564 (pio_reg_read(INTR_STATUS) & STAT_CMD_QUEUE_READY)) { in hci_pio_process_cmd()
615 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_queue_xfer()
690 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_dequeue_xfer()
704 if (pio_reg_read(INTR_STATUS) & STAT_RESP_READY) { in hci_pio_err()
737 pio_reg_read(INTR_STATUS), pio_reg_read(INTR_SIGNAL_ENABLE)); in hci_pio_err()
[all …]
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| H A D | core.c | 82 #define INTR_STATUS 0x20 macro
549 val = reg_read(INTR_STATUS); in i3c_hci_irq_handler()
553 reg_write(INTR_STATUS, val); in i3c_hci_irq_handler()
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| H A D | dma.c | 750 status = rh_reg_read(INTR_STATUS); in hci_dma_irq_handler()
754 rh_reg_write(INTR_STATUS, status); in hci_dma_irq_handler()
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| /openbmc/qemu/hw/i3c/ |
| H A D | aspeed_i3c.c | 177 REG32(INTR_STATUS, 0x3c)
178 FIELD(INTR_STATUS, TX_THLD, 0, 1)
179 FIELD(INTR_STATUS, RX_THLD, 1, 1)
180 FIELD(INTR_STATUS, IBI_THLD, 2, 1)
181 FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1)
182 FIELD(INTR_STATUS, RESP_RDY, 4, 1)
183 FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1)
184 FIELD(INTR_STATUS, CCC_UPDATED, 6, 1)
185 FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1)
186 FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1)
[all …]
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | denali_spl.c | 45 intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank)); in wait_for_irq()
109 writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank)); in denali_send_pipeline_cmd()
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| H A D | denali.h | 205 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) macro
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| H A D | denali.c | 149 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq()
166 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in __denali_check_irq()
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| /openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hwio.h | 15 #define INTR_STATUS 0x014 macro
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| H A D | dpu_hw_interrupts.c | 60 INTR_STATUS
131 INTR_STATUS
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| /openbmc/linux/drivers/net/phy/ |
| H A D | bcm-phy-ptp.c | 67 #define INTR_STATUS 0x085f macro
236 reg = bcm_phy_read_exp(phydev, INTR_STATUS); in bcm_ptp_framesync_ts()
427 reg = bcm_phy_read_exp(phydev, INTR_STATUS); in bcm_ptp_get_tstamp()
649 reg = bcm_phy_read_exp(phydev, INTR_STATUS); in bcm_ptp_extts_work()
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| /openbmc/linux/drivers/media/platform/nvidia/tegra-vde/ |
| H A D | h264.c | 120 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
127 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
137 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
303 tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); in tegra_vde_setup_hw_context()
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| H A D | vde.h | 30 #define INTR_STATUS 0x18 macro
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| /openbmc/linux/drivers/i3c/master/ |
| H A D | dw-i3c-master.c | 115 #define INTR_STATUS 0x3c macro
643 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_bus_init()
1374 status = readl(master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1377 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1384 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); in dw_i3c_master_irq_handler()
1486 writel(INTR_ALL, master->regs + INTR_STATUS); in dw_i3c_common_probe()
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | denali.h | 208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) macro
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| H A D | cadence-nand-controller.c | 65 #define INTR_STATUS 0x0110 macro
728 writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_clear_interrupt()
739 irq_status->status = readl_relaxed(cdns_ctrl->reg + INTR_STATUS); in cadence_nand_read_int_status()
1183 writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_hw_init()
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| H A D | denali.c | 111 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); in denali_clear_irq()
132 irq_status = ioread32(denali->reg + INTR_STATUS(i)); in denali_isr()
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