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Searched refs:INTER_REGS_BASE (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr_ml_wrapper.h17 #define INTER_REGS_BASE SOC_REGS_PHY_BASE macro
130 writel(val, INTER_REGS_BASE + addr); in reg_write()
135 return readl(INTER_REGS_BASE + addr); in reg_read()
140 setbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_set()
145 clrbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_clr()
H A Dmv_ddr_plat.h17 #define INTER_REGS_BASE SOC_REGS_PHY_BASE macro
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.h124 writel(val, INTER_REGS_BASE + addr); in reg_write()
129 return readl(INTER_REGS_BASE + addr); in reg_read()
134 setbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_set()
139 clrbits_le32(INTER_REGS_BASE + addr, mask); in reg_bit_clr()
H A Dddr3_axp.h78 #define INTER_REGS_BASE SOC_REGS_PHY_BASE macro
H A Dddr3_dfs.c59 writel(val, INTER_REGS_BASE + addr); in dfs_reg_write()
64 writel(val, INTER_REGS_BASE + addr); in dfs_reg_write()