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Searched refs:ICPU_RESET (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/
H A Dreset.c26 writel(readl(BASE_CFG + ICPU_RESET) | in _machine_restart()
29 BASE_CFG + ICPU_RESET); in _machine_restart()
34 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); in _machine_restart()
52 writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET); in _machine_restart()
58 clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT); in _machine_restart()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h463 writel(readl(BASE_CFG + ICPU_RESET) | in hal_vcoreiii_ddr_reset_assert()
464 ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET); in hal_vcoreiii_ddr_reset_assert()
469 writel(0, BASE_CFG + ICPU_RESET); in hal_vcoreiii_ddr_failed()
650 setbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE); in hal_vcoreiii_ddr_reset_assert()
747 clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE); in hal_vcoreiii_init_memctl()
/openbmc/u-boot/board/mscc/ocelot/
H A Docelot.c29 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); in mscc_switch_reset()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h12 #define ICPU_RESET 0x20 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h12 #define ICPU_RESET 0x20 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h12 #define ICPU_RESET 0x20 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h12 #define ICPU_RESET 0x20 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h12 #define ICPU_RESET 0x20 macro