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/openbmc/docs/architecture/code-update/
H A Dcode-update-diagrams.md3 1. [High-Level Overview](#High-Level Overview)
5 ## High-Level Overview
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dpower_distribution.hpp24 High, enumerator
64 {TransferSensitivityType::High, "High"},
/openbmc/u-boot/board/Synology/ds109/
H A Dopenocd.cfg47 mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
53 mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register
54 mww 0xD0001428 0x00085520 ;# Dunit Control High Register
55 mww 0xD000147c 0x00008552 ;# Dunit Control High Register
64 mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
H A Dkwbimage.cfg56 DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
108 DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
140 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
/openbmc/phosphor-bmc-code-mgmt/eeprom-device/
H A DREADME.md19 "Polarity": "High"
23 "Polarity": "High"
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage-memphis.cfg42 # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
76 DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
119 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
139 DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High
161 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
H A Dkwbimage.cfg39 # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
73 DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
116 DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
146 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
H A Dkwbimage_256M8_1.cfg86 # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
129 DATA 0xFFD0140C 0x0000003E # DDR Timing (High)
182 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
205 DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
238 DATA 0xFFD01498 0x00000004 # DDR ODT Control (High)
H A Dkwbimage_128M16_1.cfg86 # If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
129 DATA 0xFFD0140C 0x0000003e # DDR Timing (High)
182 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
205 DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
238 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/ntopng/files/
H A Dntopng.service2 Description=ntopng - High-Speed Web-based Traffic Analysis and Flow Collection Tool
/openbmc/u-boot/arch/arm/dts/
H A Dkirkwood-openrd.dtsi64 * High: RS-485
82 * High: SD
/openbmc/qemu/rust/hw/timer/hpet/
H A DCargo.toml5 description = "IA-PC High Precision Event Timer emulation in Rust"
/openbmc/u-boot/doc/device-tree-bindings/serial/
H A Dqca,ar9330-uart.txt1 * Qualcomm Atheros AR9330 High-Speed UART
/openbmc/u-boot/drivers/video/rockchip/
H A DKconfig15 Rockchip SoCs provide video output capabilities for High-Definition
60 This enables High-Definition Multimedia Interface display support.
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A DKconfig108 This config option enables High OPP for DSPEVE.
132 This config option enables High OPP for IVA.
156 This config option enables High OPP for GPU.
/openbmc/u-boot/board/Seagate/nas220/
H A Dkwbimage.cfg56 DATA 0xFFD0140C 0x00000819 # DDR Timing (High)
110 DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
137 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
/openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/
H A Dpython3-anyio_4.9.0.bb1 SUMMARY = "High level compatibility layer for multiple asynchronous event loop implementations"
/openbmc/u-boot/board/Seagate/dockstar/
H A Dkwbimage.cfg55 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
107 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
137 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dkwbimage.cfg58 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
110 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
140 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
/openbmc/u-boot/board/Marvell/dreamplug/
H A Dkwbimage.cfg53 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
105 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
135 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg52 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
104 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
134 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
/openbmc/u-boot/board/Marvell/guruplug/
H A Dkwbimage.cfg52 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
104 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
134 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
/openbmc/u-boot/arch/arm/mach-sti/
H A DKconfig24 - High speed connector (SD/I2C/USB interfaces)
/openbmc/u-boot/doc/device-tree-bindings/sound/
H A Dintel-hda.txt1 * Intel High-definition Audio
/openbmc/openbmc/poky/meta/recipes-multimedia/lame/
H A Dlame_3.100.bb1 SUMMARY = "High quality MP3 audio encoder"

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