1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2548c4597SSean Wang 3548c4597SSean Wangconfig MTK_HSDMA 4548c4597SSean Wang tristate "MediaTek High-Speed DMA controller support" 5548c4597SSean Wang depends on ARCH_MEDIATEK || COMPILE_TEST 6548c4597SSean Wang select DMA_ENGINE 7548c4597SSean Wang select DMA_VIRTUAL_CHANNELS 8a7f7f624SMasahiro Yamada help 9548c4597SSean Wang Enable support for High-Speed DMA controller on MediaTek 10548c4597SSean Wang SoCs. 11548c4597SSean Wang 12548c4597SSean Wang This controller provides the channels which is dedicated to 13548c4597SSean Wang memory-to-memory transfer to offload from CPU through ring- 14548c4597SSean Wang based descriptor management. 15b1f01e48SShun-Chih Yu 16b1f01e48SShun-Chih Yuconfig MTK_CQDMA 17b1f01e48SShun-Chih Yu tristate "MediaTek Command-Queue DMA controller support" 18b1f01e48SShun-Chih Yu depends on ARCH_MEDIATEK || COMPILE_TEST 19b1f01e48SShun-Chih Yu select DMA_ENGINE 20b1f01e48SShun-Chih Yu select DMA_VIRTUAL_CHANNELS 21b1f01e48SShun-Chih Yu select ASYNC_TX_ENABLE_CHANNEL_SWITCH 22b1f01e48SShun-Chih Yu help 23b1f01e48SShun-Chih Yu Enable support for Command-Queue DMA controller on MediaTek 24b1f01e48SShun-Chih Yu SoCs. 25b1f01e48SShun-Chih Yu 26b1f01e48SShun-Chih Yu This controller provides the channels which is dedicated to 27b1f01e48SShun-Chih Yu memory-to-memory transfer to offload from CPU. 289135408cSLong Cheng 299135408cSLong Chengconfig MTK_UART_APDMA 309135408cSLong Cheng tristate "MediaTek SoCs APDMA support for UART" 319135408cSLong Cheng depends on OF && SERIAL_8250_MT6577 329135408cSLong Cheng select DMA_ENGINE 339135408cSLong Cheng select DMA_VIRTUAL_CHANNELS 349135408cSLong Cheng help 359135408cSLong Cheng Support for the UART DMA engine found on MediaTek MTK SoCs. 369135408cSLong Cheng When SERIAL_8250_MT6577 is enabled, and if you want to use DMA, 379135408cSLong Cheng you can enable the config. The DMA engine can only be used 389135408cSLong Cheng with MediaTek SoCs. 39