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Searched refs:HHI_MPLL_CNTL9 (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_meson_axg.c43 MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
140 {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
141 {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
H A Dclk_meson.c180 MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
628 {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
629 {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.h77 #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ macro
H A Daxg.h88 #define HHI_MPLL_CNTL9 0x2A0 macro
H A Dgxbb.h82 #define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */ macro
H A Daxg.c592 .reg_off = HHI_MPLL_CNTL9,
597 .reg_off = HHI_MPLL_CNTL9,
602 .reg_off = HHI_MPLL_CNTL9,
631 .offset = HHI_MPLL_CNTL9,
H A Dgxbb.c844 .reg_off = HHI_MPLL_CNTL9,
849 .reg_off = HHI_MPLL_CNTL9,
854 .reg_off = HHI_MPLL_CNTL9,
872 .offset = HHI_MPLL_CNTL9,
H A Dmeson8b.c571 .reg_off = HHI_MPLL_CNTL9,
576 .reg_off = HHI_MPLL_CNTL9,
581 .reg_off = HHI_MPLL_CNTL9,
599 .offset = HHI_MPLL_CNTL9,
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h87 #define HHI_MPLL_CNTL9 0x2A0 macro
H A Dclock-gx.h82 #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ macro