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Searched refs:HHI_MPLL_CNTL8 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.h76 #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ macro
H A Daxg.h87 #define HHI_MPLL_CNTL8 0x29C macro
H A Dgxbb.h81 #define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */ macro
H A Dg12a.h102 #define HHI_MPLL_CNTL8 0x298 macro
H A Daxg.c541 .reg_off = HHI_MPLL_CNTL8,
546 .reg_off = HHI_MPLL_CNTL8,
551 .reg_off = HHI_MPLL_CNTL8,
575 .offset = HHI_MPLL_CNTL8,
H A Dgxbb.c801 .reg_off = HHI_MPLL_CNTL8,
806 .reg_off = HHI_MPLL_CNTL8,
811 .reg_off = HHI_MPLL_CNTL8,
829 .offset = HHI_MPLL_CNTL8,
H A Dmeson8b.c526 .reg_off = HHI_MPLL_CNTL8,
531 .reg_off = HHI_MPLL_CNTL8,
536 .reg_off = HHI_MPLL_CNTL8,
554 .offset = HHI_MPLL_CNTL8,
H A Dg12a.c2364 { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h86 #define HHI_MPLL_CNTL8 0x29C macro
H A Dclock-gx.h81 #define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */ macro
/openbmc/u-boot/drivers/clk/
H A Dclk_meson_axg.c135 {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
136 {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
H A Dclk_meson.c179 MESON_GATE(CLKID_MPLL1, HHI_MPLL_CNTL8, 14),
623 {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
624 {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */