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Searched refs:HHI_MPLL_CNTL7 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.h75 #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ macro
H A Daxg.h86 #define HHI_MPLL_CNTL7 0x298 macro
H A Dgxbb.h80 #define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */ macro
H A Dg12a.h101 #define HHI_MPLL_CNTL7 0x294 macro
H A Daxg.c490 .reg_off = HHI_MPLL_CNTL7,
495 .reg_off = HHI_MPLL_CNTL7,
500 .reg_off = HHI_MPLL_CNTL7,
524 .offset = HHI_MPLL_CNTL7,
H A Dgxbb.c720 .reg_off = HHI_MPLL_CNTL7,
730 .reg_off = HHI_MPLL_CNTL7,
749 .reg_off = HHI_MPLL_CNTL7,
754 .reg_off = HHI_MPLL_CNTL7,
759 .reg_off = HHI_MPLL_CNTL7,
777 .offset = HHI_MPLL_CNTL7,
H A Dmeson8b.c476 .reg_off = HHI_MPLL_CNTL7,
481 .reg_off = HHI_MPLL_CNTL7,
486 .reg_off = HHI_MPLL_CNTL7,
509 .offset = HHI_MPLL_CNTL7,
H A Dg12a.c2370 .reg_off = HHI_MPLL_CNTL7,
2375 .reg_off = HHI_MPLL_CNTL7,
2380 .reg_off = HHI_MPLL_CNTL7,
2385 .reg_off = HHI_MPLL_CNTL7,
2405 .offset = HHI_MPLL_CNTL7,
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h85 #define HHI_MPLL_CNTL7 0x298 macro
H A Dclock-gx.h80 #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ macro
/openbmc/u-boot/drivers/clk/
H A Dclk_meson_axg.c130 {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
131 {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
H A Dclk_meson.c178 MESON_GATE(CLKID_MPLL0, HHI_MPLL_CNTL7, 14),
618 {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
619 {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */