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Searched refs:HHI_MPLL_CNTL6 (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.h74 #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ macro
H A Daxg.h85 #define HHI_MPLL_CNTL6 0x294 macro
H A Dgxbb.h79 #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ macro
H A Dg12a.h100 #define HHI_MPLL_CNTL6 0x290 macro
H A Daxg.c339 .offset = HHI_MPLL_CNTL6,
366 .offset = HHI_MPLL_CNTL6,
404 .offset = HHI_MPLL_CNTL6,
430 .offset = HHI_MPLL_CNTL6,
458 .offset = HHI_MPLL_CNTL6,
H A Dgxbb.c573 .offset = HHI_MPLL_CNTL6,
600 .offset = HHI_MPLL_CNTL6,
638 .offset = HHI_MPLL_CNTL6,
664 .offset = HHI_MPLL_CNTL6,
690 .offset = HHI_MPLL_CNTL6,
H A Dmeson8b.c332 .offset = HHI_MPLL_CNTL6,
360 .offset = HHI_MPLL_CNTL6,
388 .offset = HHI_MPLL_CNTL6,
416 .offset = HHI_MPLL_CNTL6,
444 .offset = HHI_MPLL_CNTL6,
H A Dg12a.c2310 { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h84 #define HHI_MPLL_CNTL6 0x294 macro
H A Dclock-gx.h79 #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ macro
/openbmc/u-boot/drivers/clk/
H A Dclk_meson.c174 MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28),
175 MESON_GATE(CLKID_FCLK_DIV4, HHI_MPLL_CNTL6, 29),
176 MESON_GATE(CLKID_FCLK_DIV5, HHI_MPLL_CNTL6, 30),
177 MESON_GATE(CLKID_FCLK_DIV7, HHI_MPLL_CNTL6, 31),