Home
last modified time | relevance | path

Searched refs:HHI_MPLL_CNTL (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/clk/meson/
H A Dmeson8b.h50 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ macro
69 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ macro
H A Daxg.h80 #define HHI_MPLL_CNTL 0x280 macro
H A Dgxbb.h74 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ macro
H A Daxg.c31 .reg_off = HHI_MPLL_CNTL,
36 .reg_off = HHI_MPLL_CNTL,
41 .reg_off = HHI_MPLL_CNTL,
51 .reg_off = HHI_MPLL_CNTL,
56 .reg_off = HHI_MPLL_CNTL,
73 .offset = HHI_MPLL_CNTL,
607 .reg_off = HHI_MPLL_CNTL,
H A Dgxbb.c91 .reg_off = HHI_MPLL_CNTL,
96 .reg_off = HHI_MPLL_CNTL,
101 .reg_off = HHI_MPLL_CNTL,
111 .reg_off = HHI_MPLL_CNTL,
116 .reg_off = HHI_MPLL_CNTL,
133 .offset = HHI_MPLL_CNTL,
725 .reg_off = HHI_MPLL_CNTL,
H A Dmeson8b.c62 .reg_off = HHI_MPLL_CNTL,
67 .reg_off = HHI_MPLL_CNTL,
72 .reg_off = HHI_MPLL_CNTL,
82 .reg_off = HHI_MPLL_CNTL,
87 .reg_off = HHI_MPLL_CNTL,
106 .offset = HHI_MPLL_CNTL,
491 .reg_off = HHI_MPLL_CNTL,
/openbmc/u-boot/drivers/clk/
H A Dclk_meson_axg.c189 {HHI_MPLL_CNTL, 0, 9}, /* pm */
190 {HHI_MPLL_CNTL, 9, 5}, /* pn */
191 {HHI_MPLL_CNTL, 16, 2}, /* pod */
H A Dclk_meson.c677 {HHI_MPLL_CNTL, 0, 9}, /* pm */
678 {HHI_MPLL_CNTL, 9, 5}, /* pn */
679 {HHI_MPLL_CNTL, 16, 2}, /* pod */
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h79 #define HHI_MPLL_CNTL 0x280 macro
H A Dclock-gx.h74 #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ macro