Home
last modified time | relevance | path

Searched refs:HHI_HDMI_PLL_CNTL (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c267 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
269 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
510 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
526 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
528 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
539 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
569 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
578 HHI_HDMI_PLL_CNTL, val, in meson_hdmi_pll_set_params()
594 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
605 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vclk.c213 hhi_write(HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
219 hhi_write(HHI_HDMI_PLL_CNTL, 0x4800023d); in meson_venci_cvbs_clock_config()
222 hhi_write(HHI_HDMI_PLL_CNTL, 0x4000027b); in meson_venci_cvbs_clock_config()
230 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
232 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
239 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
397 hhi_write(HHI_HDMI_PLL_CNTL, 0x58000200 | m); in meson_hdmi_pll_set_params()
410 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
418 hhi_write(HHI_HDMI_PLL_CNTL, 0x40000200 | m); in meson_hdmi_pll_set_params()
426 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
[all …]
/openbmc/linux/drivers/clk/meson/
H A Dgxbb.h97 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ macro
H A Dgxbb.c168 .reg_off = HHI_HDMI_PLL_CNTL,
173 .reg_off = HHI_HDMI_PLL_CNTL,
178 .reg_off = HHI_HDMI_PLL_CNTL,
188 .reg_off = HHI_HDMI_PLL_CNTL,
193 .reg_off = HHI_HDMI_PLL_CNTL,
216 .reg_off = HHI_HDMI_PLL_CNTL,
221 .reg_off = HHI_HDMI_PLL_CNTL,
226 .reg_off = HHI_HDMI_PLL_CNTL,
242 .reg_off = HHI_HDMI_PLL_CNTL,
247 .reg_off = HHI_HDMI_PLL_CNTL,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-gx.h97 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ macro