Lines Matching refs:HHI_HDMI_PLL_CNTL
70 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ macro
213 hhi_write(HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
219 hhi_write(HHI_HDMI_PLL_CNTL, 0x4800023d); in meson_venci_cvbs_clock_config()
222 hhi_write(HHI_HDMI_PLL_CNTL, 0x4000027b); in meson_venci_cvbs_clock_config()
230 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
232 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
239 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
397 hhi_write(HHI_HDMI_PLL_CNTL, 0x58000200 | m); in meson_hdmi_pll_set_params()
410 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
414 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val, in meson_hdmi_pll_set_params()
418 hhi_write(HHI_HDMI_PLL_CNTL, 0x40000200 | m); in meson_hdmi_pll_set_params()
426 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
428 hhi_update_bits(HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
432 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val, in meson_hdmi_pll_set_params()