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Searched refs:GENMASK (Results 1 – 25 of 161) sorted by relevance

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/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
41 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
42 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
45 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
55 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
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H A Docelot_devcpu_gcb_miim_regs.h16 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
17 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
18 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
19 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
22 #define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h37 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
38 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
39 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
40 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
41 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
50 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
51 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
52 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
53 #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
54 #define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
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H A Dserval_devcpu_gcb_miim_regs.h16 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
17 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
18 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
19 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
22 #define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h29 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 6) & GENMASK(7, 6))
30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(7, 6)
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4)
32 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4))
33 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_M GENMASK(5, 4)
34 #define ICPU_GENERAL_CTRL_IF_SI1_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
44 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
45 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
46 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
47 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
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H A Djr2_devcpu_gcb_miim_regs.h16 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
17 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
18 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
19 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
22 #define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h30 #define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 4) & GENMASK(5, 4))
31 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(5, 4)
32 #define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
42 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
44 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
45 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
46 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
55 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
56 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
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H A Dservalt_devcpu_gcb_miim_regs.h16 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & ((x) << 25))
17 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & ((x) << 20))
18 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & ((x) << 4))
19 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & ((x) << 1))
22 #define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
23 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) (((x) >> 0) & GENMASK(15, 0))
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h35 #define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
36 #define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
41 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
42 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
43 #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
44 #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
45 #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
54 #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
55 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
56 #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
[all …]
H A Dluton_devcpu_gcb_miim_regs.h18 #define MSCC_F_MII_CMD_MIIM_CMD_PHYAD(x) (GENMASK(29, 25) & (x << 25))
19 #define MSCC_F_MII_CMD_MIIM_CMD_REGAD(x) (GENMASK(24, 20) & (x << 20))
20 #define MSCC_F_MII_CMD_MIIM_CMD_WRDATA(x) (GENMASK(19, 4) & (x << 4))
21 #define MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(x) (GENMASK(2, 1) & (x << 1))
23 #define MSCC_M_MII_DATA_MIIM_DATA_SUCCESS GENMASK(17, 16)
24 #define MSCC_X_MII_DATA_MIIM_DATA_RDDATA(x) ((x >> 0) & GENMASK(15, 0))
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Ddenali.h21 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
24 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
27 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
30 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
52 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
64 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
65 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
69 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
70 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
73 #define RE_2_WE__VALUE GENMASK(5, 0)
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/openbmc/u-boot/drivers/pinctrl/aspeed/
H A Dpinctrl_ast2600.c49 { 0x418, GENMASK(9, 8), 1 },
50 { 0x4B8, GENMASK(9, 8), 0 },
54 { 0x418, GENMASK(11, 10), 1 },
55 { 0x4B8, GENMASK(11, 10), 0 },
59 { 0x418, GENMASK(13, 12), 1 },
60 { 0x4B8, GENMASK(13, 12), 0 },
64 { 0x418, GENMASK(15, 14), 1 },
65 { 0x4B8, GENMASK(15, 14), 0 },
69 { 0x418, GENMASK(17, 16), 0 },
73 { 0x418, GENMASK(19, 18), 0 },
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/openbmc/u-boot/drivers/phy/
H A Dmeson-gxl-usb3.c24 #define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
28 #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
29 #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
32 #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
33 #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
39 #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
40 #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
41 #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
45 #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
46 #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
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H A Dmeson-gxl-usb2.c42 #define U2P_R0_FSEL_MASK GENMASK(19, 17)
43 #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
45 #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
61 #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
62 #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
63 #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
64 #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
65 #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
66 #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
67 #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
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/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3368.h59 PLL_NR_MASK = GENMASK(13, 8),
61 PLL_OD_MASK = GENMASK(3, 0),
66 PLL_NF_MASK = GENMASK(12, 0),
70 PLL_BWADJ_MASK = GENMASK(11, 0),
74 PLL_MODE_MASK = GENMASK(9, 8),
80 PLL_RESET_MASK = GENMASK(5, 5),
84 MCU_STCLK_DIV_MASK = GENMASK(10, 8),
90 MCU_CLK_DIV_MASK = GENMASK(4, 0),
94 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
99 GMAC_DIV_CON_MASK = GENMASK(4, 0),
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H A Dgrf_rk3368.h108 MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
114 MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
120 MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
126 MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
128 MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
130 MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
132 MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dsd_emmc.h33 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
37 #define CFG_BL_LEN_MASK GENMASK(7, 4)
40 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
42 #define CFG_RC_CC_MASK GENMASK(15, 12)
48 #define STATUS_MASK GENMASK(15, 0)
49 #define STATUS_ERR_MASK GENMASK(12, 0)
50 #define STATUS_RXD_ERR_MASK GENMASK(7, 0)
61 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
/openbmc/u-boot/drivers/adc/
H A Dmeson-saradc.c22 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
28 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
29 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
30 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
33 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
36 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
43 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
45 (GENMASK(2, 0) << ((_chan) * 3))
51 (GENMASK(17, 16) << ((_chan) * 2))
55 (GENMASK(1, 0) << ((_chan) * 2))
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dsdram_ast2600.h43 #define MCR30_MODE_REG_SEL_MASK GENMASK(3, 1)
48 #define MCR34_SELF_REFRESH_STATUS_MASK GENMASK(30, 28)
51 #define MCR34_ODT_DELAY_MASK GENMASK(15, 12)
53 #define MCR34_ODT_EXT_MASK GENMASK(11, 10)
66 #define MCR38_RW_MAX_GRANT_CNT_RQ_MASK GENMASK(20, 16)
80 #define SDRAM_CONF_VGA_SIZE_MASK GENMASK(3, 2)
82 #define SDRAM_CONF_CAP_MASK GENMASK(1, 0)
98 #define SDRAM_REFRESH_PERIOD_ZQCS_MASK GENMASK(31, 16)
100 #define SDRAM_REFRESH_PERIOD_MASK GENMASK(15, 8)
108 #define SDRAM_WL_SETTING GENMASK(23, 20)
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/openbmc/u-boot/drivers/power/domain/
H A Dmtk-power-domain.c94 .sram_pdn_bits = GENMASK(11, 8),
100 .sram_pdn_bits = GENMASK(11, 8),
101 .sram_pdn_ack_bits = GENMASK(12, 12),
106 .sram_pdn_bits = GENMASK(11, 8),
107 .sram_pdn_ack_bits = GENMASK(12, 12),
112 .sram_pdn_bits = GENMASK(11, 8),
113 .sram_pdn_ack_bits = GENMASK(13, 12),
118 .sram_pdn_bits = GENMASK(11, 8),
123 .sram_pdn_bits = GENMASK(11, 8),
124 .sram_pdn_ack_bits = GENMASK(15, 12),
[all …]
/openbmc/u-boot/drivers/video/stm32/
H A Dstm32_ltdc.c71 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
72 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
74 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
75 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
77 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
78 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
80 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
81 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
90 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
91 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
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/openbmc/u-boot/arch/arm/mach-k3/include/mach/
H A Dam6_hardware.h15 #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0)
17 #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4)
19 #define CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK GENMASK(12, 12)
21 #define CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK GENMASK(14, 14)
23 #define CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK GENMASK(17, 17)
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr_regs.h237 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
243 #define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0)
246 #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4)
256 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
266 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16)
279 #define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8)
280 #define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0)
310 #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
314 #define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
327 #define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
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/openbmc/u-boot/arch/arm/mach-rockchip/rk3368/
H A Drk3368.c21 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
22 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
25 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
26 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
29 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
30 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
/openbmc/u-boot/include/linux/mtd/
H A Dspi-nor.h166 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
172 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
178 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
384 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
389 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
395 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
401 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
416 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
419 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
424 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)

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