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Searched refs:FSL_DDR_CACHE_LINE_INTERLEAVING (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/board/freescale/b4860qds/
H A Dddr.c219 case FSL_DDR_CACHE_LINE_INTERLEAVING: in step_assign_addresses()
/openbmc/u-boot/drivers/ddr/fsl/
H A Dmain.c331 case FSL_DDR_CACHE_LINE_INTERLEAVING: in __step_assign_addresses()
710 case FSL_DDR_CACHE_LINE_INTERLEAVING: in __fsl_ddr_sdram()
H A Dutil.c283 case FSL_DDR_CACHE_LINE_INTERLEAVING: in print_ddr_info()
H A Doptions.c1119 0 : FSL_DDR_CACHE_LINE_INTERLEAVING; in populate_memctl_options()
1367 case FSL_DDR_CACHE_LINE_INTERLEAVING: in check_interleaving_options()
H A Dctrl_regs.c178 case FSL_DDR_CACHE_LINE_INTERLEAVING: in set_csn_config()
/openbmc/u-boot/include/
H A Dfsl_ddr_sdram.h89 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 macro