1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <hwconfig.h>
9 #include <fsl_ddr.h>
10 #include <asm/mmu.h>
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 dimm_params_t ddr_raw_timing = {
18 .n_ranks = 2,
19 .rank_density = 2147483648u,
20 .capacity = 4294967296u,
21 .primary_sdram_width = 64,
22 .ec_sdram_width = 8,
23 .registered_dimm = 0,
24 .mirrored_dimm = 1,
25 .n_row_addr = 15,
26 .n_col_addr = 10,
27 .n_banks_per_sdram_device = 8,
28 .edc_config = 2, /* ECC */
29 .burst_lengths_bitmask = 0x0c,
30
31 .tckmin_x_ps = 1071,
32 .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
33 .taa_ps = 13910,
34 .twr_ps = 15000,
35 .trcd_ps = 13910,
36 .trrd_ps = 6000,
37 .trp_ps = 13910,
38 .tras_ps = 34000,
39 .trc_ps = 48910,
40 .trfc_ps = 260000,
41 .twtr_ps = 7500,
42 .trtp_ps = 7500,
43 .refresh_rate_ps = 7800000,
44 .tfaw_ps = 35000,
45 };
46
fsl_ddr_get_dimm_params(dimm_params_t * pdimm,unsigned int controller_number,unsigned int dimm_number)47 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
48 unsigned int controller_number,
49 unsigned int dimm_number)
50 {
51 const char dimm_model[] = "RAW timing DDR";
52
53 if ((controller_number == 0) && (dimm_number == 0)) {
54 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
55 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
56 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
57 }
58
59 return 0;
60 }
61
62 struct board_specific_parameters {
63 u32 n_ranks;
64 u32 datarate_mhz_high;
65 u32 clk_adjust;
66 u32 wrlvl_start;
67 u32 wrlvl_ctl_2;
68 u32 wrlvl_ctl_3;
69 u32 cpo;
70 u32 write_data_delay;
71 u32 force_2t;
72 };
73
74 /*
75 * This table contains all valid speeds we want to override with board
76 * specific parameters. datarate_mhz_high values need to be in ascending order
77 * for each n_ranks group.
78 */
79 static const struct board_specific_parameters udimm0[] = {
80 /*
81 * memory controller 0
82 * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
83 * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
84 */
85 {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
86 {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
87 {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
88 {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
89 {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
90 {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
91 {}
92 };
93
94 static const struct board_specific_parameters *udimms[] = {
95 udimm0,
96 };
97
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)98 void fsl_ddr_board_options(memctl_options_t *popts,
99 dimm_params_t *pdimm,
100 unsigned int ctrl_num)
101 {
102 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
103 ulong ddr_freq;
104
105 if (ctrl_num > 2) {
106 printf("Not supported controller number %d\n", ctrl_num);
107 return;
108 }
109 if (!pdimm->n_ranks)
110 return;
111
112 pbsp = udimms[0];
113
114
115 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
116 * freqency and n_banks specified in board_specific_parameters table.
117 */
118 ddr_freq = get_ddr_freq(0) / 1000000;
119 while (pbsp->datarate_mhz_high) {
120 if (pbsp->n_ranks == pdimm->n_ranks) {
121 if (ddr_freq <= pbsp->datarate_mhz_high) {
122 popts->cpo_override = pbsp->cpo;
123 popts->write_data_delay =
124 pbsp->write_data_delay;
125 popts->clk_adjust = pbsp->clk_adjust;
126 popts->wrlvl_start = pbsp->wrlvl_start;
127 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
128 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
129 popts->twot_en = pbsp->force_2t;
130 goto found;
131 }
132 pbsp_highest = pbsp;
133 }
134 pbsp++;
135 }
136
137 if (pbsp_highest) {
138 printf("Error: board specific timing not found "
139 "for data rate %lu MT/s\n"
140 "Trying to use the highest speed (%u) parameters\n",
141 ddr_freq, pbsp_highest->datarate_mhz_high);
142 popts->cpo_override = pbsp_highest->cpo;
143 popts->write_data_delay = pbsp_highest->write_data_delay;
144 popts->clk_adjust = pbsp_highest->clk_adjust;
145 popts->wrlvl_start = pbsp_highest->wrlvl_start;
146 popts->twot_en = pbsp_highest->force_2t;
147 } else {
148 panic("DIMM is not supported by this board");
149 }
150 found:
151 /*
152 * Factors to consider for half-strength driver enable:
153 * - number of DIMMs installed
154 */
155 popts->half_strength_driver_enable = 0;
156 /*
157 * Write leveling override
158 */
159 popts->wrlvl_override = 1;
160 popts->wrlvl_sample = 0xf;
161
162 /*
163 * Rtt and Rtt_WR override
164 */
165 popts->rtt_override = 0;
166
167 /* Enable ZQ calibration */
168 popts->zq_en = 1;
169
170 /* DHC_EN =1, ODT = 75 Ohm */
171 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
172 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
173
174 /* optimize cpo for erratum A-009942 */
175 popts->cpo_sample = 0x3e;
176 }
177
dram_init(void)178 int dram_init(void)
179 {
180 phys_size_t dram_size;
181
182 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
183 puts("Initializing....using SPD\n");
184 dram_size = fsl_ddr_sdram();
185 #else
186 dram_size = fsl_ddr_sdram_size();
187 #endif
188 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
189 dram_size *= 0x100000;
190
191 gd->ram_size = dram_size;
192
193 return 0;
194 }
195
step_assign_addresses(fsl_ddr_info_t * pinfo,unsigned int dbw_cap_adj[])196 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
197 unsigned int dbw_cap_adj[])
198 {
199 int i, j;
200 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
201 unsigned long long rank_density, ctlr_density = 0;
202
203 current_mem_base = 0ull;
204 total_mem = 0;
205 /*
206 * This board has soldered DDR chips. DDRC1 has two rank.
207 * DDRC2 has only one rank.
208 * Assigning DDRC2 to lower address and DDRC1 to higher address.
209 */
210 if (pinfo->memctl_opts[0].memctl_interleaving) {
211 rank_density = pinfo->dimm_params[0][0].rank_density >>
212 dbw_cap_adj[0];
213 ctlr_density = rank_density;
214
215 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
216 rank_density, ctlr_density);
217 for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
218 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
219 case FSL_DDR_CACHE_LINE_INTERLEAVING:
220 case FSL_DDR_PAGE_INTERLEAVING:
221 case FSL_DDR_BANK_INTERLEAVING:
222 case FSL_DDR_SUPERBANK_INTERLEAVING:
223 total_ctlr_mem = 2 * ctlr_density;
224 break;
225 default:
226 panic("Unknown interleaving mode");
227 }
228 pinfo->common_timing_params[i].base_address =
229 current_mem_base;
230 pinfo->common_timing_params[i].total_mem =
231 total_ctlr_mem;
232 total_mem = current_mem_base + total_ctlr_mem;
233 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
234 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
235 }
236 } else {
237 /*
238 * Simple linear assignment if memory
239 * controllers are not interleaved.
240 */
241 for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
242 total_ctlr_mem = 0;
243 pinfo->common_timing_params[i].base_address =
244 current_mem_base;
245 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
246 /* Compute DIMM base addresses. */
247 unsigned long long cap =
248 pinfo->dimm_params[i][j].capacity;
249 pinfo->dimm_params[i][j].base_address =
250 current_mem_base;
251 debug("ctrl %d dimm %d base 0x%llx\n",
252 i, j, current_mem_base);
253 current_mem_base += cap;
254 total_ctlr_mem += cap;
255 }
256 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
257 pinfo->common_timing_params[i].total_mem =
258 total_ctlr_mem;
259 total_mem += total_ctlr_mem;
260 }
261 }
262 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
263
264 return total_mem;
265 }
266