Searched refs:FR_PLL_DIV1 (Results 1 – 1 of 1) sorted by relevance
39 #define FR_PLL_DIV1 0x1d macro123 ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a); in meson_gxl_config_init()