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Searched refs:FR_PLL_DIV1 (Results 1 – 1 of 1) sorted by relevance

/openbmc/linux/drivers/net/phy/
H A Dmeson-gxl.c39 #define FR_PLL_DIV1 0x1d macro
123 ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a); in meson_gxl_config_init()