1a2443fd1SAndrew Lunn // SPDX-License-Identifier: GPL-2.0+
27334b3e4SNeil Armstrong /*
37334b3e4SNeil Armstrong * Amlogic Meson GXL Internal PHY Driver
47334b3e4SNeil Armstrong *
57334b3e4SNeil Armstrong * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
67334b3e4SNeil Armstrong * Copyright (C) 2016 BayLibre, SAS. All rights reserved.
77334b3e4SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com>
87334b3e4SNeil Armstrong */
97334b3e4SNeil Armstrong #include <linux/kernel.h>
107334b3e4SNeil Armstrong #include <linux/module.h>
117334b3e4SNeil Armstrong #include <linux/mii.h>
127334b3e4SNeil Armstrong #include <linux/ethtool.h>
137334b3e4SNeil Armstrong #include <linux/phy.h>
147334b3e4SNeil Armstrong #include <linux/netdevice.h>
15f1e2400aSJerome Brunet #include <linux/bitfield.h>
16be66fcc1SHeiner Kallweit #include <linux/smscphy.h>
177334b3e4SNeil Armstrong
1800fd73ebSJerome Brunet #define TSTCNTL 20
1900fd73ebSJerome Brunet #define TSTCNTL_READ BIT(15)
2000fd73ebSJerome Brunet #define TSTCNTL_WRITE BIT(14)
2100fd73ebSJerome Brunet #define TSTCNTL_REG_BANK_SEL GENMASK(12, 11)
2200fd73ebSJerome Brunet #define TSTCNTL_TEST_MODE BIT(10)
2300fd73ebSJerome Brunet #define TSTCNTL_READ_ADDRESS GENMASK(9, 5)
2400fd73ebSJerome Brunet #define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0)
2500fd73ebSJerome Brunet #define TSTREAD1 21
2600fd73ebSJerome Brunet #define TSTWRITE 23
27a502a8f0SHeiner Kallweit
2800fd73ebSJerome Brunet #define BANK_ANALOG_DSP 0
2900fd73ebSJerome Brunet #define BANK_WOL 1
3000fd73ebSJerome Brunet #define BANK_BIST 3
3100fd73ebSJerome Brunet
3200fd73ebSJerome Brunet /* WOL Registers */
3300fd73ebSJerome Brunet #define LPI_STATUS 0xc
3400fd73ebSJerome Brunet #define LPI_STATUS_RSV12 BIT(12)
3500fd73ebSJerome Brunet
3600fd73ebSJerome Brunet /* BIST Registers */
3700fd73ebSJerome Brunet #define FR_PLL_CONTROL 0x1b
3800fd73ebSJerome Brunet #define FR_PLL_DIV0 0x1c
3900fd73ebSJerome Brunet #define FR_PLL_DIV1 0x1d
4000fd73ebSJerome Brunet
meson_gxl_open_banks(struct phy_device * phydev)41fdaa84c3SJerome Brunet static int meson_gxl_open_banks(struct phy_device *phydev)
42fdaa84c3SJerome Brunet {
43fdaa84c3SJerome Brunet int ret;
44fdaa84c3SJerome Brunet
45fdaa84c3SJerome Brunet /* Enable Analog and DSP register Bank access by
46fdaa84c3SJerome Brunet * toggling TSTCNTL_TEST_MODE bit in the TSTCNTL register
47fdaa84c3SJerome Brunet */
48fdaa84c3SJerome Brunet ret = phy_write(phydev, TSTCNTL, 0);
49fdaa84c3SJerome Brunet if (ret)
50fdaa84c3SJerome Brunet return ret;
51fdaa84c3SJerome Brunet ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
52fdaa84c3SJerome Brunet if (ret)
53fdaa84c3SJerome Brunet return ret;
54fdaa84c3SJerome Brunet ret = phy_write(phydev, TSTCNTL, 0);
55fdaa84c3SJerome Brunet if (ret)
56fdaa84c3SJerome Brunet return ret;
57fdaa84c3SJerome Brunet return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
58fdaa84c3SJerome Brunet }
59fdaa84c3SJerome Brunet
meson_gxl_close_banks(struct phy_device * phydev)60fdaa84c3SJerome Brunet static void meson_gxl_close_banks(struct phy_device *phydev)
61fdaa84c3SJerome Brunet {
62fdaa84c3SJerome Brunet phy_write(phydev, TSTCNTL, 0);
63fdaa84c3SJerome Brunet }
64fdaa84c3SJerome Brunet
meson_gxl_read_reg(struct phy_device * phydev,unsigned int bank,unsigned int reg)65fdaa84c3SJerome Brunet static int meson_gxl_read_reg(struct phy_device *phydev,
66fdaa84c3SJerome Brunet unsigned int bank, unsigned int reg)
67fdaa84c3SJerome Brunet {
68fdaa84c3SJerome Brunet int ret;
69fdaa84c3SJerome Brunet
70fdaa84c3SJerome Brunet ret = meson_gxl_open_banks(phydev);
71fdaa84c3SJerome Brunet if (ret)
72fdaa84c3SJerome Brunet goto out;
73fdaa84c3SJerome Brunet
74fdaa84c3SJerome Brunet ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ |
75fdaa84c3SJerome Brunet FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
76fdaa84c3SJerome Brunet TSTCNTL_TEST_MODE |
77fdaa84c3SJerome Brunet FIELD_PREP(TSTCNTL_READ_ADDRESS, reg));
78fdaa84c3SJerome Brunet if (ret)
79fdaa84c3SJerome Brunet goto out;
80fdaa84c3SJerome Brunet
81fdaa84c3SJerome Brunet ret = phy_read(phydev, TSTREAD1);
82fdaa84c3SJerome Brunet out:
83fdaa84c3SJerome Brunet /* Close the bank access on our way out */
84fdaa84c3SJerome Brunet meson_gxl_close_banks(phydev);
85fdaa84c3SJerome Brunet return ret;
86fdaa84c3SJerome Brunet }
87fdaa84c3SJerome Brunet
meson_gxl_write_reg(struct phy_device * phydev,unsigned int bank,unsigned int reg,uint16_t value)88fdaa84c3SJerome Brunet static int meson_gxl_write_reg(struct phy_device *phydev,
89fdaa84c3SJerome Brunet unsigned int bank, unsigned int reg,
90fdaa84c3SJerome Brunet uint16_t value)
91fdaa84c3SJerome Brunet {
92fdaa84c3SJerome Brunet int ret;
93fdaa84c3SJerome Brunet
94fdaa84c3SJerome Brunet ret = meson_gxl_open_banks(phydev);
95fdaa84c3SJerome Brunet if (ret)
96fdaa84c3SJerome Brunet goto out;
97fdaa84c3SJerome Brunet
98fdaa84c3SJerome Brunet ret = phy_write(phydev, TSTWRITE, value);
99fdaa84c3SJerome Brunet if (ret)
100fdaa84c3SJerome Brunet goto out;
101fdaa84c3SJerome Brunet
102fdaa84c3SJerome Brunet ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE |
103fdaa84c3SJerome Brunet FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
104fdaa84c3SJerome Brunet TSTCNTL_TEST_MODE |
105fdaa84c3SJerome Brunet FIELD_PREP(TSTCNTL_WRITE_ADDRESS, reg));
106fdaa84c3SJerome Brunet
107fdaa84c3SJerome Brunet out:
108fdaa84c3SJerome Brunet /* Close the bank access on our way out */
109fdaa84c3SJerome Brunet meson_gxl_close_banks(phydev);
110fdaa84c3SJerome Brunet return ret;
111fdaa84c3SJerome Brunet }
112fdaa84c3SJerome Brunet
meson_gxl_config_init(struct phy_device * phydev)1137334b3e4SNeil Armstrong static int meson_gxl_config_init(struct phy_device *phydev)
1147334b3e4SNeil Armstrong {
1159042b46eSJerome Brunet int ret;
1169042b46eSJerome Brunet
1177334b3e4SNeil Armstrong /* Enable fractional PLL */
118fdaa84c3SJerome Brunet ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_CONTROL, 0x5);
1199042b46eSJerome Brunet if (ret)
1209042b46eSJerome Brunet return ret;
1217334b3e4SNeil Armstrong
1227334b3e4SNeil Armstrong /* Program fraction FR_PLL_DIV1 */
123fdaa84c3SJerome Brunet ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a);
1249042b46eSJerome Brunet if (ret)
1259042b46eSJerome Brunet return ret;
1267334b3e4SNeil Armstrong
1277334b3e4SNeil Armstrong /* Program fraction FR_PLL_DIV1 */
128fdaa84c3SJerome Brunet ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa);
1299042b46eSJerome Brunet if (ret)
1309042b46eSJerome Brunet return ret;
1317334b3e4SNeil Armstrong
132c227ce44SHeiner Kallweit return 0;
1337334b3e4SNeil Armstrong }
1347334b3e4SNeil Armstrong
135f1e2400aSJerome Brunet /* This function is provided to cope with the possible failures of this phy
136f1e2400aSJerome Brunet * during aneg process. When aneg fails, the PHY reports that aneg is done
137f1e2400aSJerome Brunet * but the value found in MII_LPA is wrong:
138f1e2400aSJerome Brunet * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
139f1e2400aSJerome Brunet * the link partner (LP) supports aneg but the LP never acked our base
140f1e2400aSJerome Brunet * code word, it is likely that we never sent it to begin with.
141f1e2400aSJerome Brunet * - Late failures: MII_LPA is filled with a value which seems to make sense
142f1e2400aSJerome Brunet * but it actually is not what the LP is advertising. It seems that we
143f1e2400aSJerome Brunet * can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
144f1e2400aSJerome Brunet * If this particular bit is not set when aneg is reported being done,
145f1e2400aSJerome Brunet * it means MII_LPA is likely to be wrong.
146f1e2400aSJerome Brunet *
147f1e2400aSJerome Brunet * In both case, forcing a restart of the aneg process solve the problem.
148f1e2400aSJerome Brunet * When this failure happens, the first retry is usually successful but,
149f1e2400aSJerome Brunet * in some cases, it may take up to 6 retries to get a decent result
150f1e2400aSJerome Brunet */
meson_gxl_read_status(struct phy_device * phydev)1513b3397e2SColin Ian King static int meson_gxl_read_status(struct phy_device *phydev)
152f1e2400aSJerome Brunet {
153f1e2400aSJerome Brunet int ret, wol, lpa, exp;
154f1e2400aSJerome Brunet
155f1e2400aSJerome Brunet if (phydev->autoneg == AUTONEG_ENABLE) {
156f1e2400aSJerome Brunet ret = genphy_aneg_done(phydev);
157f1e2400aSJerome Brunet if (ret < 0)
158f1e2400aSJerome Brunet return ret;
159f1e2400aSJerome Brunet else if (!ret)
160f1e2400aSJerome Brunet goto read_status_continue;
161f1e2400aSJerome Brunet
162fdaa84c3SJerome Brunet /* Aneg is done, let's check everything is fine */
163fdaa84c3SJerome Brunet wol = meson_gxl_read_reg(phydev, BANK_WOL, LPI_STATUS);
164f1e2400aSJerome Brunet if (wol < 0)
165f1e2400aSJerome Brunet return wol;
166f1e2400aSJerome Brunet
167f1e2400aSJerome Brunet lpa = phy_read(phydev, MII_LPA);
168f1e2400aSJerome Brunet if (lpa < 0)
169f1e2400aSJerome Brunet return lpa;
170f1e2400aSJerome Brunet
171f1e2400aSJerome Brunet exp = phy_read(phydev, MII_EXPANSION);
172f1e2400aSJerome Brunet if (exp < 0)
173f1e2400aSJerome Brunet return exp;
174f1e2400aSJerome Brunet
17500fd73ebSJerome Brunet if (!(wol & LPI_STATUS_RSV12) ||
176f1e2400aSJerome Brunet ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
177f1e2400aSJerome Brunet /* Looks like aneg failed after all */
178f1e2400aSJerome Brunet phydev_dbg(phydev, "LPA corruption - aneg restart\n");
179f1e2400aSJerome Brunet return genphy_restart_aneg(phydev);
180f1e2400aSJerome Brunet }
181f1e2400aSJerome Brunet }
182f1e2400aSJerome Brunet
183f1e2400aSJerome Brunet read_status_continue:
184f1e2400aSJerome Brunet return genphy_read_status(phydev);
185f1e2400aSJerome Brunet }
186f1e2400aSJerome Brunet
1877334b3e4SNeil Armstrong static struct phy_driver meson_gxl_phy[] = {
1887334b3e4SNeil Armstrong {
189fad137c4SJerome Brunet PHY_ID_MATCH_EXACT(0x01814400),
1907334b3e4SNeil Armstrong .name = "Meson GXL Internal PHY",
191dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */
192a4307c0eSHeiner Kallweit .flags = PHY_IS_INTERNAL,
193f2f98c1dSTimotej Lazar .soft_reset = genphy_soft_reset,
1947334b3e4SNeil Armstrong .config_init = meson_gxl_config_init,
195f1e2400aSJerome Brunet .read_status = meson_gxl_read_status,
196be66fcc1SHeiner Kallweit .config_intr = smsc_phy_config_intr,
197be66fcc1SHeiner Kallweit .handle_interrupt = smsc_phy_handle_interrupt,
1987334b3e4SNeil Armstrong .suspend = genphy_suspend,
1997334b3e4SNeil Armstrong .resume = genphy_resume,
20069ff53e4SHeiner Kallweit .read_mmd = genphy_read_mmd_unsupported,
20169ff53e4SHeiner Kallweit .write_mmd = genphy_write_mmd_unsupported,
2025c3407abSJerome Brunet }, {
2035c3407abSJerome Brunet PHY_ID_MATCH_EXACT(0x01803301),
2045c3407abSJerome Brunet .name = "Meson G12A Internal PHY",
205dcdecdcfSHeiner Kallweit /* PHY_BASIC_FEATURES */
2065c3407abSJerome Brunet .flags = PHY_IS_INTERNAL,
207be66fcc1SHeiner Kallweit .probe = smsc_phy_probe,
208be66fcc1SHeiner Kallweit .config_init = smsc_phy_config_init,
2095c3407abSJerome Brunet .soft_reset = genphy_soft_reset,
210be66fcc1SHeiner Kallweit .read_status = lan87xx_read_status,
211be66fcc1SHeiner Kallweit .config_intr = smsc_phy_config_intr,
212be66fcc1SHeiner Kallweit .handle_interrupt = smsc_phy_handle_interrupt,
213*992e7690SHeiner Kallweit
214*992e7690SHeiner Kallweit .get_tunable = smsc_phy_get_tunable,
215*992e7690SHeiner Kallweit .set_tunable = smsc_phy_set_tunable,
216*992e7690SHeiner Kallweit
2175c3407abSJerome Brunet .suspend = genphy_suspend,
2185c3407abSJerome Brunet .resume = genphy_resume,
219afc2336fSChris Healy .read_mmd = genphy_read_mmd_unsupported,
220afc2336fSChris Healy .write_mmd = genphy_write_mmd_unsupported,
2217334b3e4SNeil Armstrong },
2227334b3e4SNeil Armstrong };
2237334b3e4SNeil Armstrong
2247334b3e4SNeil Armstrong static struct mdio_device_id __maybe_unused meson_gxl_tbl[] = {
225fad137c4SJerome Brunet { PHY_ID_MATCH_VENDOR(0x01814400) },
2265c3407abSJerome Brunet { PHY_ID_MATCH_VENDOR(0x01803301) },
2277334b3e4SNeil Armstrong { }
2287334b3e4SNeil Armstrong };
2297334b3e4SNeil Armstrong
2307334b3e4SNeil Armstrong module_phy_driver(meson_gxl_phy);
2317334b3e4SNeil Armstrong
2327334b3e4SNeil Armstrong MODULE_DEVICE_TABLE(mdio, meson_gxl_tbl);
2337334b3e4SNeil Armstrong
2347334b3e4SNeil Armstrong MODULE_DESCRIPTION("Amlogic Meson GXL Internal PHY driver");
2357334b3e4SNeil Armstrong MODULE_AUTHOR("Baoqi wang");
2367334b3e4SNeil Armstrong MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
237afb4fa47SJerome Brunet MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
2387334b3e4SNeil Armstrong MODULE_LICENSE("GPL");
239