Searched refs:FR_PLL_DIV0 (Results 1 – 1 of 1) sorted by relevance
38 #define FR_PLL_DIV0 0x1c macro128 ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa); in meson_gxl_config_init()