Home
last modified time | relevance | path

Searched refs:FIFO (Results 1 – 25 of 31) sorted by relevance

12

/openbmc/qemu/scripts/qemu-guest-agent/fsfreeze-hook.d/
H A Dmysql-flush.sh.sample9 FIFO=/var/run/mysql-flush.fifo
17 read < $FIFO
19 rm -f $FIFO
24 mkfifo $FIFO || exit 1
49 [ ! -p $FIFO ] && exit 1
50 echo > $FIFO
/openbmc/qemu/hw/misc/
H A Dmips_itu.c195 if (c->tag.FIFO) { in view_bypass_read()
204 if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) { in view_bypass_write()
218 (c->tag.FIFO << ITC_CELL_TAG_FIFO) | in view_control_read()
241 if (!c->tag.FIFO) { in view_ef_common_read()
281 if (!c->tag.FIFO) { in view_ef_common_write()
322 if (c->tag.FIFO) { in view_pv_common_read()
347 if (c->tag.FIFO) { in view_pv_common_write()
487 s->cell[i].tag.FIFO = 1; in itc_reset_cells()
H A Dmax78000_aes.c51 case FIFO: in max78000_aes_read()
129 case FIFO: in max78000_aes_write()
/openbmc/qemu/hw/i3c/
H A Dtrace-events15 dw_i3c_pop_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from RX FIFO"
17 dw_i3c_push_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to TX FIFO"
18 dw_i3c_pop_tx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] pop 0x%" PRIx32 " from TX FIFO"
19 dw_i3c_push_rx(uint32_t deviceid, uint32_t data) "I3C Dev[%u] push 0x%" PRIx32 " to RX FIFO"
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-cadence.txt9 - cdns,fifo-depth : Size of the data FIFO in words.
10 - cdns,fifo-width : Bus width of the data FIFO in bytes.
/openbmc/qemu/hw/char/
H A Dtrace-events63 pl011_read_fifo(unsigned rx_fifo_used, size_t rx_fifo_depth) "RX FIFO read, used %u/%zu"
65 …o_used, size_t rx_fifo_depth, unsigned rx_fifo_available) "LCR 0x%02x, RX FIFO used %u/%zu, can_re…
66 pl011_fifo_rx_put(uint32_t c, unsigned read_count, size_t rx_fifo_depth) "RX FIFO push char [0x%02x…
67 pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set"
96 exynos_uart_rx_fifo_reset(uint32_t channel) "UART%d: Rx FIFO Reset"
97 exynos_uart_tx_fifo_reset(uint32_t channel) "UART%d: Tx FIFO Reset"
104 exynos_uart_rxsize(uint32_t channel, uint32_t size) "UART%d: Rx FIFO size: %d"
/openbmc/qemu/include/hw/misc/
H A Dmax78000_aes.h22 #define FIFO 0x10 macro
H A Dmips_itu.h36 uint8_t FIFO; /* 1 - FIFO cell, 0 - Semaphore cell */ member
/openbmc/qemu/hw/sd/
H A Dtrace-events68 pl181_fifo_push(uint32_t data) "FIFO push 0x%08" PRIx32
69 pl181_fifo_pop(uint32_t data) "FIFO pop 0x%08" PRIx32
70 pl181_fifo_transfer_complete(void) "FIFO transfer complete"
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt20 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
21 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
H A Dti,dp83867.txt9 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
/openbmc/u-boot/arch/arm/include/asm/ti-common/
H A Dti-edma3.h41 FIFO = 1 enumerator
/openbmc/u-boot/drivers/usb/musb-new/
H A DKconfig63 All data is copied between memory and FIFO by the CPU.
/openbmc/qemu/contrib/plugins/
H A Dcache.c30 FIFO, enumerator
323 case FIFO: in get_replaced_block()
725 case FIFO: in policy_init()
806 policy = FIFO; in qemu_plugin_install()
/openbmc/u-boot/board/freescale/mx6memcal/
H A DKconfig187 read data from the internal FIFO.
197 read data from the internal FIFO
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/lmbench/lmbench/
H A D0001-doc-Fix-typos-in-manual-pages.patch50 lat_fifo \- FIFO benchmark
/openbmc/qemu/rust/hw/char/pl011/src/
H A Dregisters.rs253 FIFO = 1, enumerator
H A Ddevice.rs436 self.line_control.fifos_enabled() == registers::Mode::FIFO in fifo_enabled()
/openbmc/u-boot/drivers/dma/
H A Dti-edma3.c100 if (mode == FIFO) in edma3_set_dest()
171 if (mode == FIFO) in edma3_set_src()
/openbmc/qemu/docs/system/arm/
H A Dnuvoton.rst67 * BIOS POST code FIFO
/openbmc/u-boot/drivers/i2c/
H A DKconfig430 bool "UniPhier FIFO-builtin I2C driver"
434 Support for UniPhier FIFO-builtin I2C controller driver.
/openbmc/qemu/hw/scsi/
H A Dtrace-events159 esp_error_fifo_overrun(void) "FIFO overrun"
186 esp_mem_writeb_cmd_flush(uint32_t val) "Flush FIFO (0x%2.2x)"
/openbmc/u-boot/drivers/spi/
H A DKconfig282 controller support 8 bit SPI transfers only, with or w/o FIFO.
/openbmc/qemu/hw/usb/
H A Dtrace-events228 usb_dwc2_hreg2_read(uint64_t addr, uint64_t fifo, uint32_t val) " 0x%04" PRIx64 " FIFO%" PRId64 " …
229 …64_t fifo, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " FIFO%" PRId64 " val …
/openbmc/qemu/hw/display/
H A Dtrace-events27 vmware_update_rect_delayed_flush(void) "display update FIFO full - forcing flush"

12