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Searched refs:FIELD_DP32 (Results 1 – 25 of 61) sorted by relevance

123

/openbmc/qemu/target/loongarch/
H A Dcpu.c439 data = FIELD_DP32(data, CPUCFG1, ARCH, 2); in loongarch_la464_initfn()
440 data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); in loongarch_la464_initfn()
441 data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); in loongarch_la464_initfn()
448 data = FIELD_DP32(data, CPUCFG1, PALEN, field); in loongarch_la464_initfn()
449 data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); in loongarch_la464_initfn()
450 data = FIELD_DP32(data, CPUCFG1, UAL, 1); in loongarch_la464_initfn()
451 data = FIELD_DP32(data, CPUCFG1, RI, 1); in loongarch_la464_initfn()
452 data = FIELD_DP32(data, CPUCFG1, EP, 1); in loongarch_la464_initfn()
453 data = FIELD_DP32(data, CPUCFG1, RPLV, 1); in loongarch_la464_initfn()
454 data = FIELD_DP32(data, CPUCFG1, HP, 1); in loongarch_la464_initfn()
[all …]
H A Dcpu.h58 (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
62 (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \
68 (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
74 (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
79 (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvbf16.c.inc77 data = FIELD_DP32(data, VDATA, VM, a->vm);
78 data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
79 data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
80 data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
102 data = FIELD_DP32(data, VDATA, VM, a->vm);
103 data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
104 data = FIELD_DP32(data, VDATA, VTA, ctx->vta);
105 data = FIELD_DP32(data, VDATA, VMA, ctx->vma);
131 data = FIELD_DP32(data, VDATA, VM, a->vm);
132 data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
[all …]
H A Dtrans_rvvk.c.inc168 data = FIELD_DP32(data, VDATA, VM, a->vm); \
169 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
170 data = FIELD_DP32(data, VDATA, VTA, s->vta); \
171 data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
172 data = FIELD_DP32(data, VDATA, VMA, s->vma); \
257 data = FIELD_DP32(data, VDATA, VM, a->vm); \
258 data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
259 data = FIELD_DP32(data, VDATA, VTA, s->vta); \
260 data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \
261 data = FIELD_DP32(data, VDATA, VMA, s->vma); \
[all …]
H A Dtrans_rvv.c.inc764 data = FIELD_DP32(data, VDATA, VM, a->vm);
765 data = FIELD_DP32(data, VDATA, LMUL, emul);
766 data = FIELD_DP32(data, VDATA, NF, a->nf);
767 data = FIELD_DP32(data, VDATA, VTA, s->vta);
768 data = FIELD_DP32(data, VDATA, VMA, s->vma);
803 data = FIELD_DP32(data, VDATA, VM, a->vm);
804 data = FIELD_DP32(data, VDATA, LMUL, emul);
805 data = FIELD_DP32(data, VDATA, NF, a->nf);
830 data = FIELD_DP32(data, VDATA, LMUL, 0);
831 data = FIELD_DP32(data, VDATA, NF, 1);
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c30 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ in aa32_max_features()
31 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ in aa32_max_features()
32 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ in aa32_max_features()
33 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); in aa32_max_features()
34 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ in aa32_max_features()
35 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ in aa32_max_features()
39 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ in aa32_max_features()
40 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ in aa32_max_features()
41 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ in aa32_max_features()
42 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ in aa32_max_features()
[all …]
/openbmc/qemu/target/rx/
H A Dcpu.h159 psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl); in rx_cpu_pack_psw()
160 psw = FIELD_DP32(psw, PSW, PM, env->psw_pm); in rx_cpu_pack_psw()
161 psw = FIELD_DP32(psw, PSW, U, env->psw_u); in rx_cpu_pack_psw()
162 psw = FIELD_DP32(psw, PSW, I, env->psw_i); in rx_cpu_pack_psw()
163 psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31); in rx_cpu_pack_psw()
164 psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31); in rx_cpu_pack_psw()
165 psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0); in rx_cpu_pack_psw()
166 psw = FIELD_DP32(psw, PSW, C, env->psw_c); in rx_cpu_pack_psw()
H A Dop_helper.c65 env->fpsw = FIELD_DP32(env->fpsw, FPSW, C ## b, 1); \
67 env->fpsw = FIELD_DP32(env->fpsw, FPSW, F ## b, 1); \
82 env->fpsw = FIELD_DP32(env->fpsw, FPSW, CAUSE, 0); in update_fpsw()
104 env->fpsw = FIELD_DP32(env->fpsw, FPSW, CE, 1); in update_fpsw()
109 env->fpsw = FIELD_DP32(env->fpsw, FPSW, FS, 1); in update_fpsw()
134 FIELD_DP32(fpsw, FPSW, FS, FIELD_EX32(fpsw, FPSW, FLAGS) != 0); in helper_set_fpsw()
/openbmc/qemu/hw/ssi/
H A Dibex_spi_host.c115 data = FIELD_DP32(data, STATUS, RXFULL, 0); in ibex_spi_rxfifo_reset()
116 data = FIELD_DP32(data, STATUS, RXEMPTY, 1); in ibex_spi_rxfifo_reset()
125 data = FIELD_DP32(data, STATUS, TXFULL, 0); in ibex_spi_txfifo_reset()
126 data = FIELD_DP32(data, STATUS, TXEMPTY, 1); in ibex_spi_txfifo_reset()
272 data = FIELD_DP32(data, STATUS, READY, 1); in ibex_spi_host_transfer()
274 data = FIELD_DP32(data, STATUS, RXQD, div4_round_up(segment_len)); in ibex_spi_host_transfer()
276 data = FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / 4); in ibex_spi_host_transfer()
278 data = FIELD_DP32(data, STATUS, TXFULL, 0); in ibex_spi_host_transfer()
280 data = FIELD_DP32(data, STATUS, RXEMPTY, 0); in ibex_spi_host_transfer()
360 data = FIELD_DP32(data, INTR_STATE, ERROR, 0); in ibex_spi_host_write()
[all …]
/openbmc/qemu/tests/qtest/
H A Dsifive-e-aon-watchdog-test.c196 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, i); in test_scaled_wdogs()
218 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 0); in test_watchdog()
219 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1); in test_watchdog()
240 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0); in test_watchdog()
260 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 15); in test_scaled_watchdog()
261 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1); in test_scaled_watchdog()
282 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0); in test_scaled_watchdog()
302 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 0); in test_periodic_int()
303 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, ZEROCMP, 1); in test_periodic_int()
304 cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1); in test_periodic_int()
[all …]
H A Dufs-test.c137 ufs_wreg(ufs, A_IS, FIELD_DP32(0, IS, UTRCS, 1)); in __ufs_send_transfer_request_doorbell()
163 ufs_wreg(ufs, A_IS, FIELD_DP32(0, IS, CQES, 1)); in __ufs_send_transfer_request_mcq()
356 hce = FIELD_DP32(hce, HCE, HCE, 1); in ufs_init()
368 ie = FIELD_DP32(ie, IE, UCCE, 1); in ufs_init()
369 ie = FIELD_DP32(ie, IE, UHESE, 1); in ufs_init()
370 ie = FIELD_DP32(ie, IE, UHXSE, 1); in ufs_init()
371 ie = FIELD_DP32(ie, IE, UPMSE, 1); in ufs_init()
385 ufs_wreg(ufs, A_IS, FIELD_DP32(0, IS, UCCS, 1)); in ufs_init()
401 ie = FIELD_DP32(ie, IE, UTRCE, 1); in ufs_init()
402 ie = FIELD_DP32(ie, IE, UEE, 1); in ufs_init()
[all …]
/openbmc/qemu/hw/ppc/
H A Dmpc8544_guts.c84 value = FIELD_DP32(value, GUTS_PORPLLSR, E500_1_RATIO, 6); /* 3:1 */ in mpc8544_guts_read()
85 value = FIELD_DP32(value, GUTS_PORPLLSR, E500_0_RATIO, 6); /* 3:1 */ in mpc8544_guts_read()
86 value = FIELD_DP32(value, GUTS_PORPLLSR, DDR_RATIO, 12); /* 12:1 */ in mpc8544_guts_read()
87 value = FIELD_DP32(value, GUTS_PORPLLSR, PLAT_RATIO, 6); /* 6:1 */ in mpc8544_guts_read()
/openbmc/qemu/hw/pci/
H A Dpcie_doe.c264 *buf = FIELD_DP32(*buf, PCI_DOE_CAP_REG, INTR_SUPP, in pcie_doe_read_config()
266 *buf = FIELD_DP32(*buf, PCI_DOE_CAP_REG, DOE_INTR_MSG_NUM, in pcie_doe_read_config()
270 *buf = FIELD_DP32(*buf, PCI_DOE_CAP_CONTROL, DOE_INTR_EN, in pcie_doe_read_config()
273 *buf = FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DOE_BUSY, in pcie_doe_read_config()
275 *buf = FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DOE_INTR_STATUS, in pcie_doe_read_config()
277 *buf = FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DOE_ERROR, in pcie_doe_read_config()
279 *buf = FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DATA_OBJ_RDY, in pcie_doe_read_config()
/openbmc/qemu/target/arm/
H A Dcpu.c2125 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ in arm_cpu_realizefn()
2137 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); in arm_cpu_realizefn()
2138 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); in arm_cpu_realizefn()
2142 u = FIELD_DP32(u, MVFR0, FPSP, 0); in arm_cpu_realizefn()
2143 u = FIELD_DP32(u, MVFR0, FPDP, 0); in arm_cpu_realizefn()
2144 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); in arm_cpu_realizefn()
2145 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); in arm_cpu_realizefn()
2146 u = FIELD_DP32(u, MVFR0, FPROUND, 0); in arm_cpu_realizefn()
2148 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); in arm_cpu_realizefn()
2149 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); in arm_cpu_realizefn()
[all …]
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c126 flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); in riscv_get_tb_cpu_state()
127 flags = FIELD_DP32(flags, TB_FLAGS, SEW, vsew); in riscv_get_tb_cpu_state()
128 flags = FIELD_DP32(flags, TB_FLAGS, LMUL, in riscv_get_tb_cpu_state()
130 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); in riscv_get_tb_cpu_state()
131 flags = FIELD_DP32(flags, TB_FLAGS, VTA, in riscv_get_tb_cpu_state()
133 flags = FIELD_DP32(flags, TB_FLAGS, VMA, in riscv_get_tb_cpu_state()
135 flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0); in riscv_get_tb_cpu_state()
137 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1); in riscv_get_tb_cpu_state()
146 flags = FIELD_DP32(flags, TB_FLAGS, FCFI_LP_EXPECTED, env->elp); in riscv_get_tb_cpu_state()
147 flags = FIELD_DP32(flags, TB_FLAGS, FCFI_ENABLED, 1); in riscv_get_tb_cpu_state()
[all …]
/openbmc/qemu/hw/cxl/
H A Dcxl-component-utils.c112 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); in dumb_hdm_handler()
113 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); in dumb_hdm_handler()
115 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, ERR, 0); in dumb_hdm_handler()
116 value = FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0); in dumb_hdm_handler()
325 reg_state[which] = FIELD_DP32(reg_state[which], \ in cxl_component_register_init_common()
328 FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, \ in cxl_component_register_init_common()
331 FIELD_DP32(reg_state[which], CXL_##reg##_CAPABILITY_HEADER, PTR, \ in cxl_component_register_init_common()
/openbmc/qemu/hw/ufs/
H A Dufs.c372 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, DP, 1); in ufs_process_uiccmd()
373 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UTRLRDY, 1); in ufs_process_uiccmd()
374 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UTMRLRDY, 1); in ufs_process_uiccmd()
379 u->reg.is = FIELD_DP32(u->reg.is, IS, UHES, 1); in ufs_process_uiccmd()
380 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UPMCRS, UFS_PWR_LOCAL); in ufs_process_uiccmd()
384 u->reg.is = FIELD_DP32(u->reg.is, IS, UHXS, 1); in ufs_process_uiccmd()
385 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UPMCRS, UFS_PWR_LOCAL); in ufs_process_uiccmd()
392 u->reg.is = FIELD_DP32(u->reg.is, IS, UCCS, 1); in ufs_process_uiccmd()
477 FIELD_DP32(u->mcq_op_reg[cq->cqid].cq_int.is, CQIS, TEPS, 1); in ufs_mcq_process_cq()
479 u->reg.is = FIELD_DP32(u->reg.is, IS, CQES, 1); in ufs_mcq_process_cq()
[all …]
/openbmc/qemu/hw/arm/
H A Dsmmuv3.c264 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S2P, 1); in smmuv3_init_regs()
266 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); in smmuv3_init_regs()
267 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S2P, 1); in smmuv3_init_regs()
269 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); in smmuv3_init_regs()
272 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */ in smmuv3_init_regs()
273 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */ in smmuv3_init_regs()
274 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */ in smmuv3_init_regs()
275 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, VMID16, 1); /* 16-bit VMID */ in smmuv3_init_regs()
276 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */ in smmuv3_init_regs()
277 s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */ in smmuv3_init_regs()
[all …]
/openbmc/qemu/hw/misc/
H A Dsifive_e_aon.c85 r->wdogcfg = FIELD_DP32(r->wdogcfg, AON_WDT_WDOGCFG, IP0, 1); in sifive_e_aon_wdt_update_state()
268 r->wdogcfg = FIELD_DP32(r->wdogcfg, AON_WDT_WDOGCFG, RSTEN, 0); in sifive_e_aon_reset()
269 r->wdogcfg = FIELD_DP32(r->wdogcfg, AON_WDT_WDOGCFG, EN_ALWAYS, 0); in sifive_e_aon_reset()
270 r->wdogcfg = FIELD_DP32(r->wdogcfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE, 0); in sifive_e_aon_reset()
H A Dxlnx-versal-cframe-reg.c222 val = FIELD_DP32(val, LAST_FRAME_BOT0, BLOCKTYPE1_LAST_FRAME_LSB, in cfrm_last_frame_bot_post_read()
224 val = FIELD_DP32(val, LAST_FRAME_BOT0, BLOCKTYPE0_LAST_FRAME, in cfrm_last_frame_bot_post_read()
228 val = FIELD_DP32(val, LAST_FRAME_BOT1, BLOCKTYPE3_LAST_FRAME_LSB, in cfrm_last_frame_bot_post_read()
230 val = FIELD_DP32(val, LAST_FRAME_BOT1, BLOCKTYPE2_LAST_FRAME, in cfrm_last_frame_bot_post_read()
232 val = FIELD_DP32(val, LAST_FRAME_BOT1, BLOCKTYPE1_LAST_FRAME_MSB, in cfrm_last_frame_bot_post_read()
236 val = FIELD_DP32(val, LAST_FRAME_BOT2, BLOCKTYPE3_LAST_FRAME_MSB, in cfrm_last_frame_bot_post_read()
255 val = FIELD_DP32(val, LAST_FRAME_TOP0, BLOCKTYPE5_LAST_FRAME_LSB, in cfrm_last_frame_top_post_read()
257 val = FIELD_DP32(val, LAST_FRAME_TOP0, BLOCKTYPE4_LAST_FRAME, in cfrm_last_frame_top_post_read()
261 val = FIELD_DP32(val, LAST_FRAME_TOP1, BLOCKTYPE6_LAST_FRAME, in cfrm_last_frame_top_post_read()
263 val = FIELD_DP32(val, LAST_FRAME_TOP1, BLOCKTYPE5_LAST_FRAME_MSB, in cfrm_last_frame_top_post_read()
/openbmc/qemu/target/tricore/
H A Dhelper.c172 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _ ## FEATURE, val); \
174 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _13, val); \
180 env->REG = FIELD_DP32(env->REG, REG, FIELD, val); \
/openbmc/qemu/hw/rtc/
H A Dls7a_rtc.c117 val = FIELD_DP32(val, TOY, MON, tm->tm_mon + 1); in toy_time_to_val_mon()
118 val = FIELD_DP32(val, TOY, DAY, tm->tm_mday); in toy_time_to_val_mon()
119 val = FIELD_DP32(val, TOY, HOUR, tm->tm_hour); in toy_time_to_val_mon()
120 val = FIELD_DP32(val, TOY, MIN, tm->tm_min); in toy_time_to_val_mon()
121 val = FIELD_DP32(val, TOY, SEC, tm->tm_sec); in toy_time_to_val_mon()
/openbmc/qemu/target/loongarch/kvm/
H A Dkvm.c694 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, FP_VER, 1); in kvm_check_cpucfg2()
699 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LLFTP_VER, 1); in kvm_check_cpucfg2()
948 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 0); in kvm_cpu_check_lsx()
951 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1); in kvm_cpu_check_lsx()
957 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1); in kvm_cpu_check_lsx()
970 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 0); in kvm_cpu_check_lasx()
973 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1); in kvm_cpu_check_lasx()
979 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1); in kvm_cpu_check_lasx()
994 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7); in kvm_cpu_check_lbt()
1000 env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LBT_ALL, 7); in kvm_cpu_check_lbt()
[all …]
/openbmc/qemu/hw/i3c/
H A Ddw-i3c.c533 val = FIELD_DP32(val, DEVICE_CTRL, I3C_RESUME, 0); in dw_i3c_ctrl_w()
542 val = FIELD_DP32(val, DEVICE_CTRL, I3C_ABORT, 0); in dw_i3c_ctrl_w()
624 s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, in dw_i3c_handle_hj()
650 s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, in dw_i3c_handle_ctlr_req()
679 s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, in dw_i3c_handle_targ_irq()
697 s->ibi_data.ibi_queue_status = FIELD_DP32(s->ibi_data.ibi_queue_status, in dw_i3c_ibi_handle()
758 FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, in dw_i3c_ibi_queue_push()
769 FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, in dw_i3c_ibi_queue_push()
773 FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, in dw_i3c_ibi_queue_push()
777 FIELD_DP32(s->ibi_data.ibi_queue_status, IBI_QUEUE_STATUS, in dw_i3c_ibi_queue_push()
[all …]
/openbmc/qemu/hw/net/can/
H A Dxlnx-versal-canfd.c941 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID, in frame_to_reg_id()
943 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID_EXT, in frame_to_reg_id()
945 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, IDE, 1); in frame_to_reg_id()
946 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); in frame_to_reg_id()
948 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, RTR_RRS, 1); in frame_to_reg_id()
951 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, ID, in frame_to_reg_id()
954 id_reg_val |= FIELD_DP32(0, RB_ID_REGISTER, SRR_RTR_RRS, 1); in frame_to_reg_id()
1013 dlc_reg_val = FIELD_DP32(0, RB_DLC_REGISTER, DLC, can_len2dlc(dlc)); in store_rx_sequential()
1016 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, FDF, 1); in store_rx_sequential()
1019 dlc_reg_val |= FIELD_DP32(0, RB_DLC_REGISTER, BRS, 1); in store_rx_sequential()
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