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Searched refs:EMC_DYCS0_BASE (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c67 readl(EMC_DYCS0_BASE | dram->mode); in ddr_init()
70 readl(EMC_DYCS0_BASE | dram->emode); in ddr_init()
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h44 #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ macro
/openbmc/u-boot/include/configs/
H A Dwork_92105.h32 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
H A Ddevkit3250.h27 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE