Searched refs:EMAC0_RESET (Results 1 – 14 of 14) sorted by relevance
| /openbmc/linux/include/dt-bindings/reset/ |
| H A D | altr,rst-mgr.h | 17 #define EMAC0_RESET 32 macro
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| H A D | altr,rst-mgr-s10.h | 19 #define EMAC0_RESET 32 macro
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| H A D | altr,rst-mgr-a10.h | 16 #define EMAC0_RESET 32 macro
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| /openbmc/u-boot/include/dt-bindings/reset/ |
| H A D | altr,rst-mgr.h | 17 #define EMAC0_RESET 32 macro
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| H A D | altr,rst-mgr-s10.h | 18 #define EMAC0_RESET 32 macro
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| H A D | altr,rst-mgr-a10.h | 24 #define EMAC0_RESET 32 macro
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| /openbmc/u-boot/arch/arm/mach-socfpga/ |
| H A D | misc_s10.c | 102 gmac_index = args.args[0] - EMAC0_RESET; in socfpga_set_phymode()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | socfpga_stratix10.dtsi | 96 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
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| H A D | socfpga_arria10.dtsi | 448 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
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| H A D | socfpga.dtsi | 555 resets = <&rst EMAC0_RESET>;
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| /openbmc/linux/arch/arm64/boot/dts/altera/ |
| H A D | socfpga_stratix10.dtsi | 155 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
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| /openbmc/linux/arch/arm64/boot/dts/intel/ |
| H A D | socfpga_agilex.dtsi | 160 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
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| /openbmc/linux/arch/arm/boot/dts/intel/socfpga/ |
| H A D | socfpga.dtsi | 578 resets = <&rst EMAC0_RESET>;
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| H A D | socfpga_arria10.dtsi | 442 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
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