19c92ab61SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 216fb4f8bSSteffen Trumtrar /* 316fb4f8bSSteffen Trumtrar * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 416fb4f8bSSteffen Trumtrar */ 516fb4f8bSSteffen Trumtrar 616fb4f8bSSteffen Trumtrar #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H 716fb4f8bSSteffen Trumtrar #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H 816fb4f8bSSteffen Trumtrar 916fb4f8bSSteffen Trumtrar /* MPUMODRST */ 1016fb4f8bSSteffen Trumtrar #define CPU0_RESET 0 1116fb4f8bSSteffen Trumtrar #define CPU1_RESET 1 1216fb4f8bSSteffen Trumtrar #define WDS_RESET 2 1316fb4f8bSSteffen Trumtrar #define SCUPER_RESET 3 1416fb4f8bSSteffen Trumtrar #define L2_RESET 4 1516fb4f8bSSteffen Trumtrar 1616fb4f8bSSteffen Trumtrar /* PERMODRST */ 1716fb4f8bSSteffen Trumtrar #define EMAC0_RESET 32 1816fb4f8bSSteffen Trumtrar #define EMAC1_RESET 33 1916fb4f8bSSteffen Trumtrar #define USB0_RESET 34 2016fb4f8bSSteffen Trumtrar #define USB1_RESET 35 2116fb4f8bSSteffen Trumtrar #define NAND_RESET 36 2216fb4f8bSSteffen Trumtrar #define QSPI_RESET 37 2316fb4f8bSSteffen Trumtrar #define L4WD0_RESET 38 2416fb4f8bSSteffen Trumtrar #define L4WD1_RESET 39 2516fb4f8bSSteffen Trumtrar #define OSC1TIMER0_RESET 40 2616fb4f8bSSteffen Trumtrar #define OSC1TIMER1_RESET 41 2716fb4f8bSSteffen Trumtrar #define SPTIMER0_RESET 42 2816fb4f8bSSteffen Trumtrar #define SPTIMER1_RESET 43 2916fb4f8bSSteffen Trumtrar #define I2C0_RESET 44 3016fb4f8bSSteffen Trumtrar #define I2C1_RESET 45 3116fb4f8bSSteffen Trumtrar #define I2C2_RESET 46 3216fb4f8bSSteffen Trumtrar #define I2C3_RESET 47 3316fb4f8bSSteffen Trumtrar #define UART0_RESET 48 3416fb4f8bSSteffen Trumtrar #define UART1_RESET 49 3516fb4f8bSSteffen Trumtrar #define SPIM0_RESET 50 3616fb4f8bSSteffen Trumtrar #define SPIM1_RESET 51 3716fb4f8bSSteffen Trumtrar #define SPIS0_RESET 52 3816fb4f8bSSteffen Trumtrar #define SPIS1_RESET 53 3916fb4f8bSSteffen Trumtrar #define SDMMC_RESET 54 4016fb4f8bSSteffen Trumtrar #define CAN0_RESET 55 4116fb4f8bSSteffen Trumtrar #define CAN1_RESET 56 4216fb4f8bSSteffen Trumtrar #define GPIO0_RESET 57 4316fb4f8bSSteffen Trumtrar #define GPIO1_RESET 58 4416fb4f8bSSteffen Trumtrar #define GPIO2_RESET 59 4516fb4f8bSSteffen Trumtrar #define DMA_RESET 60 4616fb4f8bSSteffen Trumtrar #define SDR_RESET 61 4716fb4f8bSSteffen Trumtrar 4816fb4f8bSSteffen Trumtrar /* PER2MODRST */ 4916fb4f8bSSteffen Trumtrar #define DMAIF0_RESET 64 5016fb4f8bSSteffen Trumtrar #define DMAIF1_RESET 65 5116fb4f8bSSteffen Trumtrar #define DMAIF2_RESET 66 5216fb4f8bSSteffen Trumtrar #define DMAIF3_RESET 67 5316fb4f8bSSteffen Trumtrar #define DMAIF4_RESET 68 5416fb4f8bSSteffen Trumtrar #define DMAIF5_RESET 69 5516fb4f8bSSteffen Trumtrar #define DMAIF6_RESET 70 5616fb4f8bSSteffen Trumtrar #define DMAIF7_RESET 71 5716fb4f8bSSteffen Trumtrar 5816fb4f8bSSteffen Trumtrar /* BRGMODRST */ 5916fb4f8bSSteffen Trumtrar #define HPS2FPGA_RESET 96 6016fb4f8bSSteffen Trumtrar #define LWHPS2FPGA_RESET 97 6116fb4f8bSSteffen Trumtrar #define FPGA2HPS_RESET 98 6216fb4f8bSSteffen Trumtrar 6316fb4f8bSSteffen Trumtrar /* MISCMODRST*/ 6416fb4f8bSSteffen Trumtrar #define ROM_RESET 128 6516fb4f8bSSteffen Trumtrar #define OCRAM_RESET 129 6616fb4f8bSSteffen Trumtrar #define SYSMGR_RESET 130 6716fb4f8bSSteffen Trumtrar #define SYSMGRCOLD_RESET 131 6816fb4f8bSSteffen Trumtrar #define FPGAMGR_RESET 132 6916fb4f8bSSteffen Trumtrar #define ACPIDMAP_RESET 133 7016fb4f8bSSteffen Trumtrar #define S2F_RESET 134 7116fb4f8bSSteffen Trumtrar #define S2FCOLD_RESET 135 7216fb4f8bSSteffen Trumtrar #define NRSTPIN_RESET 136 7316fb4f8bSSteffen Trumtrar #define TIMESTAMPCOLD_RESET 137 7416fb4f8bSSteffen Trumtrar #define CLKMGRCOLD_RESET 138 7516fb4f8bSSteffen Trumtrar #define SCANMGR_RESET 139 7616fb4f8bSSteffen Trumtrar #define FRZCTRLCOLD_RESET 140 7716fb4f8bSSteffen Trumtrar #define SYSDBG_RESET 141 7816fb4f8bSSteffen Trumtrar #define DBG_RESET 142 7916fb4f8bSSteffen Trumtrar #define TAPCOLD_RESET 143 8016fb4f8bSSteffen Trumtrar #define SDRCOLD_RESET 144 8116fb4f8bSSteffen Trumtrar 8216fb4f8bSSteffen Trumtrar #endif 83