19c92ab61SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2007bb689SDinh Nguyen /* 3007bb689SDinh Nguyen * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 4007bb689SDinh Nguyen */ 5007bb689SDinh Nguyen 6007bb689SDinh Nguyen #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 7007bb689SDinh Nguyen #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 8007bb689SDinh Nguyen 9007bb689SDinh Nguyen /* MPUMODRST */ 10007bb689SDinh Nguyen #define CPU0_RESET 0 11007bb689SDinh Nguyen #define CPU1_RESET 1 12007bb689SDinh Nguyen #define WDS_RESET 2 13007bb689SDinh Nguyen #define SCUPER_RESET 3 14007bb689SDinh Nguyen 15007bb689SDinh Nguyen /* PER0MODRST */ 16007bb689SDinh Nguyen #define EMAC0_RESET 32 17007bb689SDinh Nguyen #define EMAC1_RESET 33 18007bb689SDinh Nguyen #define EMAC2_RESET 34 19007bb689SDinh Nguyen #define USB0_RESET 35 20007bb689SDinh Nguyen #define USB1_RESET 36 21007bb689SDinh Nguyen #define NAND_RESET 37 22007bb689SDinh Nguyen #define QSPI_RESET 38 23007bb689SDinh Nguyen #define SDMMC_RESET 39 24007bb689SDinh Nguyen #define EMAC0_OCP_RESET 40 25007bb689SDinh Nguyen #define EMAC1_OCP_RESET 41 26007bb689SDinh Nguyen #define EMAC2_OCP_RESET 42 27007bb689SDinh Nguyen #define USB0_OCP_RESET 43 28007bb689SDinh Nguyen #define USB1_OCP_RESET 44 29007bb689SDinh Nguyen #define NAND_OCP_RESET 45 30007bb689SDinh Nguyen #define QSPI_OCP_RESET 46 31007bb689SDinh Nguyen #define SDMMC_OCP_RESET 47 32007bb689SDinh Nguyen #define DMA_RESET 48 33007bb689SDinh Nguyen #define SPIM0_RESET 49 34007bb689SDinh Nguyen #define SPIM1_RESET 50 35007bb689SDinh Nguyen #define SPIS0_RESET 51 36007bb689SDinh Nguyen #define SPIS1_RESET 52 37007bb689SDinh Nguyen #define DMA_OCP_RESET 53 38007bb689SDinh Nguyen #define EMAC_PTP_RESET 54 39007bb689SDinh Nguyen /* 55 is empty*/ 40007bb689SDinh Nguyen #define DMAIF0_RESET 56 41007bb689SDinh Nguyen #define DMAIF1_RESET 57 42007bb689SDinh Nguyen #define DMAIF2_RESET 58 43007bb689SDinh Nguyen #define DMAIF3_RESET 59 44007bb689SDinh Nguyen #define DMAIF4_RESET 60 45007bb689SDinh Nguyen #define DMAIF5_RESET 61 46007bb689SDinh Nguyen #define DMAIF6_RESET 62 47007bb689SDinh Nguyen #define DMAIF7_RESET 63 48007bb689SDinh Nguyen 49007bb689SDinh Nguyen /* PER1MODRST */ 50007bb689SDinh Nguyen #define L4WD0_RESET 64 51007bb689SDinh Nguyen #define L4WD1_RESET 65 52007bb689SDinh Nguyen #define L4SYSTIMER0_RESET 66 53007bb689SDinh Nguyen #define L4SYSTIMER1_RESET 67 54007bb689SDinh Nguyen #define SPTIMER0_RESET 68 55007bb689SDinh Nguyen #define SPTIMER1_RESET 69 56007bb689SDinh Nguyen /* 70-71 is reserved */ 57007bb689SDinh Nguyen #define I2C0_RESET 72 58007bb689SDinh Nguyen #define I2C1_RESET 73 59007bb689SDinh Nguyen #define I2C2_RESET 74 60007bb689SDinh Nguyen #define I2C3_RESET 75 61007bb689SDinh Nguyen #define I2C4_RESET 76 62007bb689SDinh Nguyen /* 77-79 is reserved */ 63007bb689SDinh Nguyen #define UART0_RESET 80 64007bb689SDinh Nguyen #define UART1_RESET 81 65007bb689SDinh Nguyen /* 82-87 is reserved */ 66007bb689SDinh Nguyen #define GPIO0_RESET 88 67007bb689SDinh Nguyen #define GPIO1_RESET 89 68007bb689SDinh Nguyen #define GPIO2_RESET 90 69007bb689SDinh Nguyen 70007bb689SDinh Nguyen /* BRGMODRST */ 71007bb689SDinh Nguyen #define HPS2FPGA_RESET 96 72007bb689SDinh Nguyen #define LWHPS2FPGA_RESET 97 73007bb689SDinh Nguyen #define FPGA2HPS_RESET 98 74007bb689SDinh Nguyen #define F2SSDRAM0_RESET 99 75007bb689SDinh Nguyen #define F2SSDRAM1_RESET 100 76007bb689SDinh Nguyen #define F2SSDRAM2_RESET 101 77007bb689SDinh Nguyen #define DDRSCH_RESET 102 78007bb689SDinh Nguyen 79007bb689SDinh Nguyen /* SYSMODRST*/ 80007bb689SDinh Nguyen #define ROM_RESET 128 81007bb689SDinh Nguyen #define OCRAM_RESET 129 82007bb689SDinh Nguyen /* 130 is reserved */ 83007bb689SDinh Nguyen #define FPGAMGR_RESET 131 84007bb689SDinh Nguyen #define S2F_RESET 132 85007bb689SDinh Nguyen #define SYSDBG_RESET 133 86007bb689SDinh Nguyen #define OCRAM_OCP_RESET 134 87007bb689SDinh Nguyen 88007bb689SDinh Nguyen /* COLDMODRST */ 89007bb689SDinh Nguyen #define CLKMGRCOLD_RESET 160 90007bb689SDinh Nguyen /* 161-162 is reserved */ 91007bb689SDinh Nguyen #define S2FCOLD_RESET 163 92007bb689SDinh Nguyen #define TIMESTAMPCOLD_RESET 164 93007bb689SDinh Nguyen #define TAPCOLD_RESET 165 94007bb689SDinh Nguyen #define HMCCOLD_RESET 166 95007bb689SDinh Nguyen #define IOMGRCOLD_RESET 167 96007bb689SDinh Nguyen 97007bb689SDinh Nguyen /* NRSTMODRST */ 98007bb689SDinh Nguyen #define NRSTPINOE_RESET 192 99007bb689SDinh Nguyen 100007bb689SDinh Nguyen /* DBGMODRST */ 101007bb689SDinh Nguyen #define DBG_RESET 224 102007bb689SDinh Nguyen #endif 103