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Searched refs:EA (Results 1 – 25 of 47) sorted by relevance

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/openbmc/qemu/target/hexagon/mmvec/
H A Dmacros.h108 #define fV_AL_CHECK(EA, MASK) \ argument
109 if ((EA) & (MASK)) { \
126 target_ulong va = EA; \
137 target_ulong va = EA; \
150 target_ulong va = EA; \
163 target_ulong va = EA; \
241 target_ulong va = EA; \
283 #define fLOADMMV(EA, DST) gen_vreg_load(ctx, DST##_off, EA, true) argument
286 #define fLOADMMVU(EA, DST) gen_vreg_load(ctx, DST##_off, EA, false) argument
289 #define fSTOREMMV(EA, SRC) \ argument
[all …]
/openbmc/qemu/target/hexagon/imported/
H A Dldst.idef45 fLOAD(1,2,u,EA,tmpV);
54 fLOAD(1,4,u,EA,tmpV);
66 fLOAD(1,2,u,EA,tmpV);
75 fLOAD(1,4,u,EA,tmpV);
87 fLOAD(1,2,u,EA,tmpV);
96 fLOAD(1,1,u,EA,tmpV);
127 …8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_LR()) << 32) | fCAST4_4u(fREAD_FP()))); fWRITE_…
151 fLOAD(1,8,u,EA,tmp);
153 fWRITE_SP(EA+8); })
157 fLOAD(1,8,u,EA,tmp);
[all …]
H A Dsubinsns.idef76 fLOAD(1,8,u,EA,tmp);
80 fWRITE_SP(EA+8); })
84 fLOAD(1,8,u,EA,tmp);
88 fWRITE_SP(EA+8);
93 fJUMPR(REG_LR,fGETWORD(1,tmp),COF_TYPE_JUMPR);} else {LOAD_CANCEL(EA);} })
97 fJUMPR(REG_LR,fGETWORD(1,tmp),COF_TYPE_JUMPR);} else {LOAD_CANCEL(EA);} })
102 …LSBNEW0) { fLOAD(1,8,u,EA,tmp); tmp = fFRAME_UNSCRAMBLE(tmp); fWRITE_LR(fGETWORD(1,tmp)); fWRITE_F…
103 fJUMPR(REG_LR,fGETWORD(1,tmp),COF_TYPE_JUMPR);} else {LOAD_CANCEL(EA);} })
106 …NEW0NOT) { fLOAD(1,8,u,EA,tmp); tmp = fFRAME_UNSCRAMBLE(tmp); fWRITE_LR(fGETWORD(1,tmp)); fWRITE_F…
107 fJUMPR(REG_LR,fGETWORD(1,tmp),COF_TYPE_JUMPR);} else {LOAD_CANCEL(EA);} })
[all …]
H A Dsystem.idef36 …)",ATTRIBS(A_ICOP,A_ICFLUSHOP),"Instruction Cache Invalidate Address",{fEA_REG(RsV); fICINVA(EA);})
43 …",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH(EA);})
46 …,A_RESTRICT_SLOT0ONLY,A_DCZEROA),"Zero an aligned 32-byte cacheline",{fEA_REG(RsV); fDCZEROA(EA);})
47 …TTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean Address",{fEA_REG(RsV); fDCCLEANA(EA);})
48 …SLOT0ONLY,A_DCFLUSHOP),"Data Cache Clean and Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);})
49 …_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),"Data Cache Invalidate Address",{fEA_REG(RsV); fDCCLEANINVA(EA);})
H A Dmacros.def870 do { EA=REG+IMM; fDOCHKPAGECROSS(REG,EA); } while (0),
876 do { EA=REG+(REG2<<SCALE); fDOCHKPAGECROSS(REG,EA); } while (0),
882 do { EA=IMM+(REG<<SCALE); fDOCHKPAGECROSS(IMM,EA); } while (0),
887 fEA_IMM, /* Calculate EA with Immediate */
888 EA=IMM,
893 fEA_REG, /* Calculate EA with REGISTER */
894 EA=REG,
900 EA=fbrev(REG),
906 do { EA=fREAD_GP()+IMM; fGP_DOCHKPAGECROSS(fREAD_GP(),EA); } while (0),
1362 sys_check_framelimit(thread,ADDR,EA),
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/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dmacros.def203 if ((EA) & (MASK)) {
204 warn("aligning misaligned vector. PC=%08x EA=%08x",thread->Regs[REG_PC],(EA));
503 fV_AL_CHECK(EA,fVECSIZE()-1);
512 fV_AL_CHECK(EA,fVECSIZE()-1);
521 fV_AL_CHECK(EA,ALIGNMENT-1);
567 if ( (EA & (fVECSIZE()-1)) == 0) {
584 fV_AL_CHECK(EA,ALIGNMENT-1);
615 fV_AL_CHECK(EA,ALIGNMENT-1);
642 if ( (EA & (fVECSIZE()-1)) == 0) {
673 if ( (EA & (fVECSIZE()-1)) == 0) {
[all …]
H A Dext.idef2354 EA = RtV+VvV.uw[i];
2367 EA = RtV+VvV.uh[i];
2385 EA = RtV+VvvV.v[j].uw[i];
2401 EA = RtV+VvV.uw[i];
2414 EA = RtV+VvV.uh[i];
2432 EA = RtV+VvvV.v[j].uw[i];
2449 EA = RtV+VvV.uw[i];
2465 EA = RtV+VvV.uh[i];
2513 EA = RtV+VvV.uw[i];
2527 EA = RtV+VvV.uh[i];
[all …]
/openbmc/qemu/target/ppc/translate/
H A Dfp-impl.c.inc799 TCGv EA;
817 TCGv EA;
834 tcg_gen_addi_tl(EA, EA, 8);
840 tcg_gen_addi_tl(EA, EA, 8);
849 TCGv EA;
866 tcg_gen_addi_tl(EA, EA, 8);
872 tcg_gen_addi_tl(EA, EA, 8);
977 tcg_gen_addi_tl(EA, EA, 8);
983 tcg_gen_addi_tl(EA, EA, 8);
1009 tcg_gen_addi_tl(EA, EA, 8);
[all …]
H A Dvsx-impl.c.inc66 tcg_gen_addi_tl(EA, EA, 8);
94 tcg_gen_addi_tl(EA, EA, 8);
100 tcg_gen_addi_tl(EA, EA, 8);
207 tcg_gen_addi_tl(EA, EA, 8);
232 tcg_gen_addi_tl(EA, EA, 8);
307 tcg_gen_addi_tl(EA, EA, 8);
336 tcg_gen_addi_tl(EA, EA, 8);
342 tcg_gen_addi_tl(EA, EA, 8);
370 tcg_gen_addi_tl(EA, EA, 8);
374 tcg_gen_addi_tl(EA, EA, 8);
[all …]
H A Dvmx-impl.c.inc30 tcg_gen_andi_tl(EA, EA, ~0xf); \
38 tcg_gen_addi_tl(EA, EA, 8); \
44 tcg_gen_addi_tl(EA, EA, 8); \
63 tcg_gen_andi_tl(EA, EA, ~0xf); \
71 tcg_gen_addi_tl(EA, EA, 8); \
77 tcg_gen_addi_tl(EA, EA, 8); \
96 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
115 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
459 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
468 TCGv EA = tcg_temp_new();
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/openbmc/qemu/target/hexagon/
H A Dmacros.h434 tcg_gen_add_tl(EA, REG, tmp); \
438 tcg_gen_shli_tl(EA, REG, SCALE); \
439 tcg_gen_addi_tl(EA, EA, IMM); \
444 EA = REG + IMM; \
448 EA = REG + (REG2 << SCALE); \
452 EA = IMM + (REG << SCALE); \
458 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG)
522 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) argument
529 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ argument
555 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot) argument
[all …]
H A Dgen_tcg.h59 gen_helper_fbrev(EA, RxV); \
70 tcg_gen_mov_tl(EA, RxV); \
77 tcg_gen_mov_tl(EA, RxV); \
114 tcg_gen_mov_tl(EA, RxV); \
164 fLOAD(1, 2, u, EA, tmp); \
216 fLOAD(1, 4, u, EA, tmp); \
266 fLOAD(1, 2, u, EA, tmp); \
295 fLOAD(1, 1, u, EA, tmp); \
332 tcg_gen_movi_tl(EA, 0); \
389 tcg_gen_movi_tl(EA, 0); \
[all …]
H A Dgenptr.c762 static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA) in gen_load_frame() argument
765 CHECK_NOSHUF(EA, 8); in gen_load_frame()
766 tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_TEUQ); in gen_load_frame()
771 static void gen_framecheck(TCGv EA, int framesize) in gen_framecheck() argument
1246 static void gen_vreg_store(DisasContext *ctx, TCGv EA, intptr_t srcoff, in gen_vreg_store() argument
1254 gen_helper_gather_store(tcg_env, EA, sl); in gen_vreg_store()
1260 tcg_gen_andi_tl(hex_vstore_addr[slot], EA, in gen_vreg_store()
1263 tcg_gen_mov_tl(hex_vstore_addr[slot], EA); in gen_vreg_store()
1273 static void gen_vreg_masked_store(DisasContext *ctx, TCGv EA, intptr_t srcoff, in gen_vreg_masked_store() argument
1280 tcg_gen_andi_tl(hex_vstore_addr[slot], EA, in gen_vreg_masked_store()
H A Dgen_tcg_hvx.h583 gen_vreg_load(ctx, DSTOFF, EA, true); \
711 gen_vreg_store(ctx, EA, OsN_off, insn->slot, true); \
748 gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \
/openbmc/qemu/target/hexagon/idef-parser/
H A Dmacros.inc107 #define fEA_RI(REG, IMM) (EA = REG + IMM)
108 #define fEA_RRs(REG, REG2, SCALE) (EA = REG + (REG2 << SCALE))
109 #define fEA_IRs(IMM, REG, SCALE) (EA = IMM + (REG << SCALE))
110 #define fEA_IMM(IMM) (EA = IMM)
111 #define fEA_REG(REG) (EA = REG)
112 #define fEA_BREVR(REG) (EA = fbrev(REG))
113 #define fEA_GPI(IMM) (EA = fREAD_GP() + IMM)
H A Didef-parser.lex314 "LOAD_CANCEL(EA)" { return LOAD_CANCEL; }
315 "STORE_CANCEL(EA)" { return STORE_CANCEL; }
/openbmc/linux/Documentation/filesystems/ext4/
H A Deainode.rst9 a regular file inode. This “EA inode” is linked only from the extended
16 and i_generation of the **one** owning inode (in cases where the EA
17 inode is not referenced by multiple inodes) to verify that the EA inode
H A Dinlinedata.rst12 “system.data” within the inode body (“ibody EA”). This of course
14 If the data size increases beyond i_block + ibody EA, a regular block
31 attribute in the inode body, the EA value is an array of
33 i_block and EA space are treated as separate dirent blocks; directory
/openbmc/qemu/target/ppc/
H A Dtranslate.c3102 tcg_gen_ext32u_tl(EA, EA); in gen_addr_imm_index()
3124 tcg_gen_ext32u_tl(EA, EA); in gen_addr_reg_index()
3808 TCGv EA; in gen_conditional_store() local
3814 EA = tcg_temp_new(); in gen_conditional_store()
3856 TCGv EA, hi, lo; in STCX() local
3866 EA = tcg_temp_new(); in STCX()
3887 TCGv EA, t0, t1; in gen_stqcx_() local
3898 EA = tcg_temp_new(); in gen_stqcx_()
5008 TCGv EA, val; in gen_dcbi()
5011 EA = tcg_temp_new(); in gen_dcbi()
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Duk-Midhurst3 # <http://www.digitaluk.co.uk/coveragechecker/main/tradeexport/GU28�9EA/NA/0/>
/openbmc/linux/drivers/tty/
H A Dn_gsm.c368 #define EA 0x01 macro
510 return c & EA; in gsm_read_ea()
826 *dp++ = (addr << 2) | (ocr << 1) | EA; in gsm_send()
830 *dp++ = EA; /* Length of data = 0 */ in gsm_send()
1102 *--dp = (msg->len << 1) | EA; in __gsm_data_queue()
1111 *--dp = (msg->addr << 2) | CR | EA; in __gsm_data_queue()
1113 *--dp = (msg->addr << 2) | EA; in __gsm_data_queue()
1206 *dp++ = (gsm_encode_modem(dlci) << 1) | EA; in gsm_dlci_data_output()
1340 *dp++ = (gsm_encode_modem(dlci) << 1) | EA; in gsm_dlci_modem_output()
1463 msg->data[1] = (dlen << 1) | EA; in gsm_control_command()
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Dtraps.c1226 unsigned long EA; in emulate_string_inst() local
1234 EA = (rA == 0) ? 0 : regs->gpr[rA]; in emulate_string_inst()
1239 EA += NB_RB; in emulate_string_inst()
1257 EA &= 0xFFFFFFFF; in emulate_string_inst()
1262 if (get_user(val, (u8 __user *)EA)) in emulate_string_inst()
1273 if (put_user(val, (u8 __user *)EA)) in emulate_string_inst()
1278 EA += 1; in emulate_string_inst()
/openbmc/linux/Documentation/arch/x86/
H A Dzero-page.rst38 1EA/001 ALL edd_mbr_sig_buf_entries Number of entries in edd_mbr_sig_buffer
/openbmc/u-boot/doc/
H A DREADME.uniphier456 This mode is the most handy because EA[24] is always supported by the save pin
457 mode of the system bus. On the other hand, EA[25] is not supported for some
458 newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S75 bic r5, r5, #0x4a @ clear IRQ, EA, nET bits

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