| /openbmc/linux/arch/arm/kernel/ |
| H A D | perf_event_v7.c | 192 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
193 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
236 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
237 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
282 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
283 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
331 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
332 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
380 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
381 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
[all …]
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| H A D | perf_event_v6.c | 109 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
110 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
172 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
173 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
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| H A D | perf_event_xscale.c | 80 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
81 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
|
| /openbmc/linux/drivers/perf/ |
| H A D | arm_pmuv3.c | 67 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
68 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
101 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
102 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
132 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
133 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
134 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
135 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
148 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
149 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
[all …]
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| H A D | riscv_pmu_sbi.c | 186 [C(DTLB)] = {
189 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
191 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
195 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
197 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
201 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
203 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}},
|
| /openbmc/linux/arch/powerpc/perf/ |
| H A D | e6500-pmu.c | 65 [C(DTLB)] = {
|
| H A D | e500-pmu.c | 66 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
| H A D | 8xx-pmu.c | 26 #define DTLB_LOAD_MISS (C(DTLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
|
| H A D | power10-pmu.c | 401 [C(DTLB)] = {
502 [C(DTLB)] = {
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| H A D | mpc7450-pmu.c | 381 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
| H A D | generic-compat-pmu.c | 228 [ C(DTLB) ] = {
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| H A D | power8-pmu.c | 309 [ C(DTLB) ] = {
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| H A D | ppc970-pmu.c | 454 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
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| H A D | power7-pmu.c | 355 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
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| H A D | power6-pmu.c | 503 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
| /openbmc/linux/arch/mips/kernel/ |
| H A D | perf_event_mipsxx.c | 1053 [C(DTLB)] = {
1182 [C(DTLB)] = {
1228 [C(DTLB)] = {
1295 [C(DTLB)] = {
1352 [C(DTLB)] = {
1452 [C(DTLB)] = {
|
| /openbmc/linux/arch/x86/events/zhaoxin/ |
| H A D | core.c | 93 [C(DTLB)] = {
197 [C(DTLB)] = {
|
| /openbmc/linux/arch/x86/events/intel/ |
| H A D | p6.c | 70 [ C(DTLB) ] = {
|
| H A D | knc.c | 73 [ C(DTLB) ] = {
|
| H A D | core.c | 509 [ C(DTLB) ] = {
669 [ C(DTLB) ] = {
903 [ C(DTLB) ] = {
1053 [ C(DTLB) ] = {
1215 [ C(DTLB) ] = {
1398 [ C(DTLB) ] = {
1503 [ C(DTLB) ] = {
1594 [ C(DTLB) ] = {
1750 [ C(DTLB) ] = {
1879 [C(DTLB)]
[all...] |
| /openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
| H A D | perf_event.c | 161 [ C(DTLB) ] = {
|
| /openbmc/linux/arch/sh/kernel/cpu/sh4/ |
| H A D | perf_event.c | 136 [ C(DTLB) ] = {
|
| /openbmc/qemu/target/xtensa/ |
| H A D | overlay_tool.h | 361 #define DTLB(varway56) \ macro
366 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
|
| /openbmc/linux/Documentation/powerpc/ |
| H A D | vcpudispatch_stats.rst | 17 By default, the DTLB log for each vcpu is processed 50 times a second so
|
| /openbmc/linux/arch/sparc/kernel/ |
| H A D | perf_event.c | 263 [C(DTLB)] = {
401 [C(DTLB)] = {
536 [C(DTLB)] = {
673 [C(DTLB)] = {
|