Searched refs:DRAM (Results 1 – 25 of 221) sorted by relevance
123456789
76 prompt "DDR4 DRAM side ODT"80 bool "DDR4 DRAM side ODT 80 ohm"83 select DDR4 DRAM side ODT 80 ohm86 bool "DDR4 DRAM side ODT 60 ohm"89 select DDR4 DRAM side ODT 60 ohm92 bool "DDR4 DRAM side ODT 48 ohm"95 select DDR4 DRAM side ODT 48 ohm98 bool "DDR4 DRAM side ODT 40 ohm"101 select DDR4 DRAM side ODT 40 ohm105 prompt "DDR4 DRAM output driver impedance"[all …]
130 When the DRAM type is DDR3, this parameter defines the ODT disable132 the ODT on the DRAM side and controller side are both disabled.138 When the DRAM type is DDR3, this parameter defines the DRAM side drive146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT180 ODT on the DRAM side and controller side are both disabled.186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT227 the ODT on the DRAM side and controller side are both disabled.233 When the DRAM type is LPDDR4, this parameter defines the DRAM side drive241 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on[all …]
17 i.MX6 CPU type and DRAM23 select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM29 select TQMa6DL with i.MX6DL and 1GiB DRAM35 select TQMa6S with i.MX6S and 512 MiB DRAM
60 on that allocates the DRAM address for each and every sensor and passes it to MP2-PCIe driver. On72 2. Data transfer via DRAM.77 the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client78 layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver79 shall allocate minimum of 32 bytes DRAM space.103 | | | Allocate the DRAM | Enable |136 | | | Read the DRAM data for| | |
112 # bit0: 0, DRAM DLL enabled113 # bit1: 1, DRAM drive strength reduced120 # bit12: 0, DRAM output buffer enabled179 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM180 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3183 # bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1194 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
112 # bit0: 0, DRAM DLL enabled113 # bit1: 1, DRAM drive strength reduced120 # bit12: 0, DRAM output buffer enabled179 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM180 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0183 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM194 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
10 DRAM, enumerator73 DRAM, enumerator113 {MemoryType::DRAM, "DRAM"},176 {MemoryMedia::DRAM, "DRAM"},
22 Tegra20 chips. The EMC controls the external DRAM on the board.34 Tegra30 chips. The EMC controls the external DRAM on the board.46 Tegra124 chips. The EMC controls the external DRAM on the board.60 Tegra210 chips. The EMC controls the external DRAM on the board.
103 # bit0: 0, DRAM DLL enabled104 # bit1: 0, DRAM drive strength normal111 # bit12: 0, DRAM output buffer enabled161 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM162 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM164 # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1165 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM174 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1175 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
13 0x00000000 0xEFFFFFFF DRAM55 0x100000000 <DRAM Size>-1 DRAM
10 E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM,19 board. The combination contains SoC, DRAM, eMMC, SD card slot,28 to a P2597 I/O board. The combination contains SoC, DRAM, eMMC, SD
7 title: Allwinner A10 DRAM PLL19 The first output is the DRAM clock output, the second is meant
134 # bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1135 # bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0136 # bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.137 # bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.141 # bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
28 outsb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_poke()64 insb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_peek()
21 The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE28 The base address of pre-allocated Trust Zone DRAM for
6 (suspend to ram), and also offloading DRAM memory clock scaling on23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
19 Frequency Scaling in DMC and DRAM. It also supports changing timings20 of DRAM running with different frequency. The timings are calculated
51 - description: DRAM controller/PHY registers63 - description: DRAM controller/PHY module clock64 - description: Register bus clock, shared by MBUS and DRAM
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
143 # bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0144 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0152 # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0153 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
138 # bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1139 # bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0140 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1141 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
135 # bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1136 # bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0137 # bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1138 # bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0