Searched refs:DPP (Results 1 – 7 of 7) sorted by relevance
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel59 want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4 DPP and 290 * DPP110 different pixel formats and outputs them to DPP in uniform streams through 4113 The Converter and Cursor (CNVC) in DPP would then normalize the data118 this floating-point format from DPP to OPP.155 MPCC: OPP DPP ...174 MPCC: OPP DPP ...180 clock frequency in the DPP part. This is not only useful for saving power but
38 * DPPCLK: DPP Clock91 DPP
64 programmed after blending, it is mapped to DPP hw blocks (pre-blending). Other183 <dc_plane_info>` input from DPP.
55 DPP = 0xa2, enumerator
403 DPP = 0xa2, enumerator756 case DPP: in complete_collecting_data()1196 case DPP: in decode_new_cmd()
563 case DPP: in xilinx_spips_num_dummies()696 case DPP: in xilinx_spips_flush_txfifo()
544 DPP = 0xa2, enumerator553 case DPP: in aspeed_smc_num_dummies()